Reiner Hartenstein*:

recent talks and keynotes

->    for a printable version of this page:  click here    <-

 

---

Reiner Hartenstein's portal page | Reiner Hartenstein's Reconfigurable Supercomputing page | Reiner Hartenstein's home page

Reconfigurable HPC;

Technical University of Talinn (TTU); May 7, 2004, Talinn, Estonia,    (ppt part 1)    (ppt part 2)    (ppt part 3)    (ppt part 4)

Software or Configware? About the Digital Divide of Computing;

18th International Parallel and Distributed Processing Symposium (IPDPS),  April 26–April 30, 2004, Santa Fe, New Mexico,  Eldorado Hotel  (ppt)

The Digital Divide of Computing;

2004 ACM International Conference on Computing Frontiers (CF04); April, 14-18, 2004. Ischia, Italy,    (ppt)   (pdf)

The Impact of Morphware on Parallel Computing;

12-th Euromicro Conference on Parallel, Distributed and Network based Processing (PDP04); February, 11-13, 2004. A Coruña, Spain,    (ppt)

Morphware: neue Perspektiven für eingebettete Systeme;

Selbstoptimierende Systeme des Maschinenbau: Workshop Selbstoptimierung und Adaption, Paderborn, Germany, 24. - 25. November 2003   (ppt)

Zusammenfassung:
Der Vortrag veranschaulicht fortgeschrittene Trends zum aktuellen neuen Paradigma der Mikroelektronik-Anwendung und deren technologische Grundlagen und gibt einen Ausblick auf deren Wirkung auf kommerzielle Infrastrukturen und die Lehrgebäude von Elektrotechnik und Informatik.

Data-Stream-Based Computing: Models and Architectural Resources;

International Conference on Microelectronics, Devices and Materials (MIDEM 2003), Ptuj, Slovenia, Oct.1-3, 2003

Abstract:
Embedded System Design often turns hardware / software co-design into hardware / configware / software co-design. The transition from HDL languages to sources of higher abstraction levels, like System-C and others, encourages to go from complex design flows to compilation techniques which are supported by a simple machine paradigm model. Because the instruction-stream-based von Neumann mind set does not support configware compilation we need a data-stream-based second model, which has been popularized recently by a number of projects in reconfigurable computing, and even for a hardwired solution. The paper introduces this anti machine model and its archtectural resources in detail.  -- ppt  --  pdf  --  fm

Using Rewriting-Logic Representation for Functional Verification in Data-Stream-Based Reconfigurable Computing

Reconfigurable Computing and its Enabling Technologies -- for the Personal Supercomputer (PS) to replace the PC;

THALES internal workshop; September 18, 2003, Orsay, France    -    ppt

Toward Reconfigurable Computing via Concussive Paradigm Shifts;

Anniversary Colloquium at Prof. Glesner's 60th Birthday;  August 29, 2003, Darmstadt, Germany. - ppt  --  * --  pdf  --  fm

Abstract:
The paper is beginning with a survey on paradigm shifts affecting academic mind sets. Then the paper points out, how reconfigurable platforms and their applications introduce fundamental padadigm shifts colliding with the tradional backgrounds of EE and CS professionals. This has a heavy impact on several areas, such as design automation, embedded system design, parallel algorithms, compilation techniques, computing machine principles and architectures and other areas. Our academic education system is heading toward a desaster, where our graduates will not be sufficiently qualified to meet the requirements of the labour market. The paper discusses proposals to solve these problems.

Reconfigurable Computing and its Compilation Techniques;

and

Distributed Memory and Datastream-based Reconfigurable Computing;

Summer School on "Multiprocessor Systems on Chip";  Örebro, Sweden, August 25-27, 2003; jointly organized by the Swedish National Program on Socware, the Strategic Integrated Electronic Systems Research Center at Linköping Universit, and the Competence Center for Circuit Design at Lund University.  - The main theme is to present fundamental issues related to the design
of multiprocessor SoCs. The main audience are the PhD students involved in these three programs. - part 1: ppt  part 2:  ppt

Reconfigurable Computing a la Mead and Conway;

Kolloquium, Informatik X: Rechnertechnik und Rechnerorganisation / Parallelrechnerarchitektur TU München;  August 21 2003, Munich, Germany. - ppt
 

Reconfigurable Computing and its Impact on SoC and beyond;

REASON Summer School on FPGA-based and Reconfigurable Systems*, University of Ljubljana, Ljubljana, Slovenia, August 11-15 August 2003.  . - ppt

Reconfigurable Computing and its Impact;

intel On Chip Reconfigurable Computing and Communication Workshop (intel ORCC workshop), Hillsboro, Oregon, USA, May 15-16, 2003 - ppt - - pps- - ppt_old_PowerPoint - - pps_old_PowerPoint

Datastream-based Reconfigurable Computing;

Dresdner Arbeitstagung Schaltungs- und Systementwurf (Workshop on Circuit and Systems Design - DASS´2003), in conjunction with  rhe Workshop System Design Automation (SDA´2003); Dresden, Germany, May, 8 - 9, 2003. . - ppt

Are we ready for the Breakthrough ?;

10th Reconfigurable Architectures Workshop 2003 (RAW 2003), Nice, France, April 22, 2003, pdf | ppt

Data-Stream-based Computing and Morphware;

Joint 33rd Speedup and 19th PARS Workshop (Speedup / PARS 2003), Basel, Switzerland, March 19 - 21, 2003, pdf | ppt

Data-stream-based Computing, Enabling Technology for Reconfigurable Computing; November 22, 2002, Seminar, EE department (ENE), University of Brasilia, Brasil, ppt

Reconfigurable Systems; November 13, 14, 21, 2002, CS department, University of Brasilia, Brasil - for similar course viewgraphs see ENST, Paris,

Panel on Embedded Architectures: Configurable, Re-configurable, or what?  (Thursday, Oct 10, session 5, 4.00 - 5.00 p.m.)

Panelists: Pierre Paulin, STMicro (moderator), Henk Corporaal, IMEC, Reiner Hartenstein, Univ. Kaiserslautern,  Oz Levia, Improv Systems,  Marco Pavesi, Italtel, Chris Rowen, Tensilica.

CASES 2002 (International Conference on Compilers, Architecture, and Syntheses for Embedded Systems), October 8-11, 2002, Grenoble, France, co-located with EMSOFT 2002 (Oct 7-9)

ppt file of the position statement: pps | Ippt
.
use PowerPoint 2002 to avoid animation bugs
 --  download Windows 2002/XP viewer

invited presentation

Trends in Reconfigurable Logic and Reconfigurable Computing;

9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia - pdf- pps - ppt - for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk   --  download Windows PowerPoint 97 viewer         2002/XP viewer

Abstract:
The paper gices a survey on Reconfigurable Logic and Reconfigurable Computing, as well as
on recent R&D trends in these areas. The paper also points out the weak aspects of recent
developments and proposes new directions to go.

invited presentation (together wirh Michael Herz (Agilent Technologies), Miguel Miranda, Erik Brockmeyer (IMEC, Leuven, Belgium), Francky Catthoor (IMEC and K.U.Leuven, Belgium):

Memory Organisation for Stream-based Reconfigurable Computing;

9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia - pdf - pps-ppt - for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk   --  download Windows 2002/XP viewer

Abstract:
The paper gives a survey on methods to cope with the memory bandwidth problem, especially
in the context of data-stream-based computing systems, like reconfigurable (and hardwired)
data path arrays, introduced by the first paper of this session and elsewhere.

keynote address

Disruptive Trends by Custom Compute Engines.

The 12th International Conference on Field Programmable Logic and Application  FPL 2002, September 2 - 4, 2002,   La Grande-Motte (Montpellier, France)

Abstract: pdf  Presentation: ppt | pps   --  download Windows   PowerPoint 97 viewer         2002/XP viewer

keynote address

Reconfigurable Computing: urging a revision of basic CS curricula.

The 15th International Conference on Systems Engineering  - ICSENG02,  Las Vegas, USA, 6-8 August, 2002 - pdf - ppt | pps

Abstract
The paper introduces the coming dichotomy of computing sciences stimulated by the emerging methodology around  reconfigurable computing and its impact on the classical mindset of controlflow-driven computing. The paper also discusses this  new methodology as a challenge to computer science and engineering curricula.

invited presentation (in German language)

Data-Stream-based Computing: Antimaterie der Informatik
(Data-Stream-based Computing: Antimatter of Informatics)

60th semester anniversary workshop of the chair "Informatik I" (Prof. Reusch), University of Dortmund, July 18. - 19, 2002 --  ppt | pps
 --  download Windows 2002/XP viewer

Abstract
It is the mission of the talk to illustrate the emerging dichotomy of computing sciences. Taking current instruction-driven mainstream computing as the world of matter in informatics, the talk introduces the data-stream-based computing methodlolgy as its world of antimatter with an antimachine paradigm and other anti issues.

invited course

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design

CNRS internal workshop, ENST, Paris, July 8 , 2002 -

prelininary versions of Powerpoint Files (will be updated after the course date): part 1, Reconfigurable Computing (RC):  ppt1  part 2, Data-Stream-based Computing:  ppt2  part 3, Resources for RC and Data-Stream-based Computing:  ppt3 part 4, Recent developments:  ppt4

keynote address

Stream-based Computing - Antimatter of Informatics;

First International Conf. on Intelligent Computing and Information Systems (ICICIS 2002), Cairo, Egypt, June 24-26, 2002. - pdf - pps  for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk

Abstract:
Recently the term "stream-based computing" has become more
popular. The paper illustrates, why stream-based computing
as the direct counterpart of von-Neumann-based concurrent
computing disrupts the fundamentals of computing science.

keynote address

Configware / Software Co-Design: Be Prepared For the Next Revolution!

The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02), Brno, Czech Republic, April 17 - 19, 2002 - pdf - pps  for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk   --  download Windows 2002/XP viewer

Abstract.
Reconfigurable computing has proceeded from niche to mainstream. This is not new any more. But now the provocative mind set, hidden behind its methodology, is heading toward a fundamental EECS curricular revolution. The talk introduces the principles of this antimatter
of computing science. However,  in contrast to particle physics, merging matter and antimatter  does not lead to annihilation, but to synergies. This provides a promising alternative to hardware software so-design: configware / software co-design

invited* presentation:
.
Stream-based Arrays: Converging Design Flows for both, Reconfigurable and Hardwired .... ;
.

invited presentation:

Reconfigurable Computing
Architectures and Methodologies for System-on-Chip

3rd Workshop.on  Enabling Technologies for System-on-Chip Development 2001   _
November 19-20, 2001,  Tampere, Finland.      -   see the program

Abstract. Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA programming is RAM-based, but by structural programming (also called "(re)configuration") instead of  procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: ready for SoC design.

Now also accelerator definition may be -at least partly- conveyed from vendor site to customer site, such as e. g. for upgrades. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods, but not really compilation. Supporting only fine-grained reconfigurability of roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methods - similar to CAD  for hardwired logic.

From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging competitor to FPGAs.  In contrast to FPGAs, the Reconfigurable Computing scene uses arrays of coarse-grained  reconfigurable datapath units (rDPUs) with drastically reduced  reconfigurability overhead: to directly configure high level parallelism. But the classical machine paradigm does not support soft datapaths because “instruction fetch” is not done at run time.

To introduce the new business model to cope with the current accelerator design crisis a transition from CAD  to compilation is needed,  and from hardware/software co-design to configware/software co-compilation.  The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.

 

Enabling Technologies for System-on-Chip Development 2001 Enabling Technologies for System-on-Chip Development 2000 Enabling Technologies for System-on-Chip Development 1999

paper (pdf), viewgraphs (ppt) (pps*)  download Windows  PowerPoint 97 viewer  2002/XP viewer   for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk ____________ *) self-executing PowerPoint Show: push     right mouse button and  select "save link as" .

invited embedded tutorial:

SBCCI 2001 - 14th Symposium on Integrated Circuits  and Systems Design *
(together with: SBMICRO - 2001   Int'l Conf. on Microelectronics and Packaging
and: SBAC-PAD 2001   13th Symp. on Computer Architecture and High Performance Computing
Pirenopolis, DF, Brazil, September 10-15, 2001, Pireneus Pousada Hotel

"Reconfigurable Computing:
the Roadmap to a New Business Model
- and its Impact on SoC Design"

Abstract. Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. But after a decade of  research on Reconfigurable Computing a new breed of reconfigurable platforms is an emerging competitor to FPGAs: coarse grained reconfigurable platforms with drastically improved efficiency.

Like microprocessor usage, also programming reconfigurable platforms is RAM-based, but by structural programming instead of  procedural programming. But so far reconfigurable platforms do not yet repeat the RAM-based success story of the software industry. Because of lacking awareness of this paradigm switch there is not yet a configware industry. A new business model is needed, as well as a fundamentally new product design flow approach.

This embedded tutorial surveys a decade of R&D on Reconfigurable Computing and related CAD. The paper illustrates, that results are available for commercialization: to cope with the current SoC design crisis by a transisiton from hardware/software co-design to to platform-based SoC design by configware/software co-compilation. The paper shows a roadmap to the success story of a coming  configware industry.

(paper: pdf, viewgraphs: ppt, download Windows Powerpoint viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer

invited embedded tutorial (keynote):

DSD'2001 - EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN:
Architectures, Methods, and Tools, Warsaw, Poland, September 4 - 6, 2001.

Reconfigurable Computing: a New Business Model - and its Impact on SoC Design

Abstract. Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA application is RAM-based, but by structural programming (also called "(re)configuration") instead of  procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design.

Now also accelerator definition may be -at least partly- conveyed from vendor site to customer site. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods.

From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging future competitor to FPGAs.  Supporting roughly single bit wide configurable logic blocks (CLBs) the  mapping tools are mainly based on gate level methods - similar to CAD  for hardwired logic. In contrast to this fine-grained reconfigurability,  the Reconfigurable Computing scene uses arrays of coarse-grained  reconfigurable datapath units (rDPUs) with drasticallyreduced  reconfigurability overhead: to directly configure high level parallelism.

But the “von Neumann” paradigm does not support soft datapaths because “instruction fetch” is not done at run time, and, since most reconfigurable computing arrays do not run parallel processes, but multiple pipe networks  instead. To introduce the new business model to cope with the current accelerator design crisis a transition from CAD to compilation is needed,  and from hardware/software co-design to configware/software co-compilation.  The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.

(paper: pdf, viewgraphs: ppt, download Windows Powerpoint viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer

DSD'2001 - EUROMICRO Symposium on Digital System Design:
Architectures, Methods, and Tools, Warsaw, Poland, September 4 - 6, 2001.

invited* embedded tutorial:

DATE 2001 -  Design, Automation and Test in Europe, Conference & Exhibition
13-16 March, 2001. ICM/Neue Messe, Munich, Germany

A Decade of Reconfigurable Computing:
A Visionary Retrospective [p. 642]

Abstract: The paper surveys a decade of R&D on coarse grain  reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of  computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.

(slides: ppt, paper: pdf, download Windows PowerPoint viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer

invited embedded tutorial:

Coarse Grain Reconfigurable Architecture

ASP-DAC 2001 - Asia and South Pacific Design Automation  Conference 2001
January 30 - February 2, 2001, Conference Center, Pacifico Yokohama, Yokohama, Japan

Abstract. The paper gives a brief survey over a decade of R&D on coarse grain reconfigurable hardware and related compilation techniques and points out its significance to the emerging discipline of reconfigurable computing.

(slides: ppt, paper:  pdf, download Windows PowerPoint  viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer

The Microprocessor is no more General Purpose: why Future Reconfigurable Platforms will win; Proceedings of the International Conference on Innovative Systems in Silicon, ISIS'97, Austin, Texas, USA, October 8-10, 1997  - pdf - htmlHonorable Mention* byE-mail

A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Future Generation Computer Systems 7 91/92, p. 181-198, North  Holland Purlishing Co. Amsterdam / New York;

Invited reprint from Proc. InfoJapan'90- (Int'l Conf. memorating the 30th Anniversary of the Computer Society of Japan), Tokyo, Japan, 1990

(with A.Hirschbiel, M. Riedmueller, K. Schmidt, M.Weber):

A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24, Hawaii Int'l. Conference on System Sciences, Koloa, Hawaii, 1991  -  pdf  -

Second Best Paper Award (Honorable Mention) -Speaker: R. Hartenstein

A Novel Asic Design Approach Based on a New Machine Paradigm; IEEE Journal of Solid State Circuits, July 1991 - ps -

Invited reprint of a paper from from Proc. ESSCIRC 1990, Geneva, Switzerland

Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Preprocessing; 12th DAGM-Symposium Mustererkennung (Pattern Recognition), Oberkochen-Aalen, Germany, 1990  -- html  -

Best Paper and Best Presentation Award (DM 1000.--) Speaker: Michael Weber

Ulrich Nageldinger: Coarse-grained Reconfigurable Architectures Design Space Exploration; Dissertation, 2001 -  pdf

Michael Herz: High Performance Memory Communication Architectures for Coarse-grained Reconfigurable Computing Systems; Dissertation 2001, Kaiserslautern University of Technology -  pdf  html

Juergen Becker: A Partitioning Compiler for Computers with Xputer-based Accelerators, Ph. D. Dissertation 1997, Kaiserslautern University of Technology  - URL - pdf

Rainer Kress: A Fast Reconfigurable ALU for Xputers, Ph. D. Dissertation 1996, Kaiserslautern University of Technology  - not available in electronic form, but you may request the printed version -- 

Remarks on the Supersystolic Array (Super systolic array): [ Google | Google2 | Wiki ]

Karin Schmidt: A Program Partitioning, Restructuring, and Mapping Method for Xputers, Ph. D. Dissertation 1994, Kaiserslautern University of Technology  - available from publisher Shaker Verlag, ISBN: 3-8265-0495-X

Reiner Hartenstein homepage

Reiner Hartenstein portal

 


© Copyright 2001, University of Kaiserslautern, Kaiserslautern, Germany Webmaster