.

Reiner Hartenstein*:

recent talks and keynotes

*) IEEE fellow [x], TU Kaiserslautern
->    for a printable version of this page:  click here    <-
 


keynotes
 
Reiner Hartenstein's portal page | Reiner Hartenstein's Reconfigurable Supercomputing page | Reiner Hartenstein's home page

Table of Contents

other pages:

[ Ph. D. theses available |MURL | serving as a panelist | interviews | talks | recent talks with abstracts | categorized talks | publicationscategorized publications | books  |  E.I.S. history | KARL history | KARL users | 2000 and earlier ]

.mainly contents of this page:

[Ph. D. theses available | MURL | List of earlier talks |  |  |  | ARC 2008 London | EU consult | SC07 Reno | Delft | Hangzhou | Antalya | Bruchsal Delft | Gent07 ITIV | Tegernsee | Ouro Preto | San Diego | Dresden | Brussels | Rhodos  | Dagstuhl06 | PASA | Mannheim | Salo | EAB | Anaheim | CapeTown | Kyushu Univ | Asia HPC 2004 | TU Tallinn | IPDPS Santa Fe | PDP04 | Selbstomptimierung | MIDEM, Ptuj | FDL | THALES, Orsay | Glesner's Birthday | summer school Oerebro, Sweden | REASON Ljubljana | Dagstuhl | Hillsboro DASS Dresden | RAW, Nice, France | PARS, Basel | Brasilia | minicourse Brasilia | CASES Grenoble | ICECS Dubrovnik | ICECS (2) | ICSENG Las Vegas | Un. Dortmund | ICICIS Cairo | DDECS BrnoVLSI-SoC Montpellier | SoC Tampere | SBCCI Brasilia | DSD Warsaw | DATE Munich | ASP-DAC Yokohama | ISIS_1997 | ARM_1996 | LIRMM_1995 | FGCS | HICSS 1991 | J.SSC | DAGM 1990 | 2000 and earlier ]

also see:

[ Ph. D. theses available | Morphware | Configware | Flowware | KressArray | Data Streams | Anti Machine | Xputers ]


2008

keynote address

The von Neumann Syndrome and the CS Education Dilemma

The  International Workshop on Applied Reconfigurable Computing (ARC 2008), March 26-38, 2008, London, UK [abstract]


2007

invited presentation

 HPC, SMEs and the price of oil;

FET (Future and Emerging Technologies) Consultation Workshop on Massive ICT Systems, Kommission of the European Union, November 27, 2007, Brussels, Belgium



invited presentation

The Neumann Syndrome calls for a revolution;

First InternationalWorkshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA'07), in conjunction with Supercomputing 2007 (SC07), 10.-17. Nov. 2007,  Reno, Nevada, USA,



invited presentation, invited paper, invited book chapter

The von Neumann Syndrome;

Stamatis Vassisliadis Memorial Symposium, Sep 28, 2007, Delft, The Netherlands


opening keynote address

Reconfigurable Computing and the von Neumann Syndrome
The 7th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), June 11 - 14, 2007, Hangzhou, China | pps  | abstract: pdf |           html

keynote panel chair (& organizer)

Transdisciplinary Science & Engineering Distinguished Keynote Panel

The 10th World Conference on Integrated Design & Process Technology (IDPT), May 27 - June 1, 2007, Antalya, Turkey   -   organized by: the Society for Design and Process Science (SDPS), and, the Software Engineering Society (SES),    --       |   |   |   |

colloquium (invited):

Computing at the Crossroads: our Skills becoming Obsolete ?
International University in Germany at Bruchsal,  March 20, 2007 pps  | abstract: pdf |           html


invited presentation

Compilation Techniques promising to bridge the Software / Configware Chasm

The  Computer Engineering Colloquium, TU Delft, Holland, February 22, 2007 pps  | abstract: pdf |           html


keynote presentation

Reconfigurable Supercomputing means to brave the Paradigm Chasm

The HiPEAC Workshop on Reconfigurable Computing, Gent, BELGIUM, January 28, 2007 pps  | abstract: pdf |           html

2006:

invited presentation

Reconfigurable Supercomputing heißt nicht nur: der Paradigmen-Kluft trotzen (Reconfigurable Supercomputing means to brave the paradigm chasm)           

Seminar, Institut für Technik der Informationsverarbeitung (ITIV), December 1, 2006, University of Karlsruhe, Germany ( pps )

invited panel contribution

Flexibility and Low Power; a Contradiction in Terms?

The 8th International Symposium on Low Power Electronics and Design 2006 (ISLPED), October 4 - 6, 2006, Tegernsee, Germany    -  press release    -   ppt  |  pdf | abstract

joint opening keynote address of SBCCI and SCMICRO

The Re-definition of Low Power Design for HPC:  a Paradigm Shift

The 19th Symposium on Integrated Circuits and System Design (SBCCI 2006), and, the 21th Symposium on Microelectronics Technology and Devices (SBMICRO 2006), August 28th - September 1st - 2006,  Ouro Preto, Minas Gerais, Brazil  (abstract: pdf | ppt | abstract | v2 )


invited presentation

Reconfigurable Supercomputing: Hurdles and Chances   

International Supercomputer Conference  (ICS 2006), June 28 - 30, 2006, Dresden, Germany (ppt | abstract)  HPCwire: txt | pdf

invited keynote panel contribution

The Transdisciplinary Responsibility of CS Curricula  

The 9th World Conference on Integrated Design & Process Technology (IDPT), June 25 - 29, 2006, San Diego, CA, USA   -    organized by: the Society for Design and Process Science (SDPS), and, the Software Engineering Society   --     ppt  |  pdfabstract

invited presentation

Reconfigurable Computing 

Computing Meeting, Commision of the EU, Brussels, Belgium, May 18, 2006,  ppt | pdf

invited keynote address

New horizons of very high performance computing (VHPC) - hurdles and chances 

The 13th Reconfigurable Architectures Workshop (RAW 2006), Rhodos Island, Greece, April 25 - 26, 2006, pdf | ppt | absract

invited talk

Reconfigurable supercomputing: What are the Problems? What are the Solutions?

Dagstuhl Seminar 06141 (06141) on Dynamically Reconfigurable Architectures, Dagstuhl Castle, Wadern, Germany, April 2 - 7, 2006, abstract | ppt1 | ppt2

invited opening keynote address

From Organic Computing to Reconfigurable Computing

8th Workshop on Parallel Systems and Algorithms (PASA 2006), March 16, 2006, Frankfurt/Main, Germany  -  in connection with the19th International Conference on Architecture of Computing Systems (ARCS 2006), March 13 - 16, 2006, Frankfurt/Main, Germany   -   pdf | ppt | absract

opening address

Why we need Reconfigurable Computing Education: Introduction

The 1st International Workshop on Reconfigurable Computing Education (RCeducation 2006), March 1, 2006, Karlsruhe, Germany  -  in connection with the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), March 2 - 3, 2006, Karlsruhe, Germany   -   pdf | ppt

 

2005:

invited presentation

Reconfigurable Supercomputing: Hindernisse und Chancen    (Reconfigurable Supercomputing: obstacles and chances);

December 13, 2005 University of Mannheim, Germany (english version: ppt)
invited presentation

CS curricula update - proposed: by adding Reconfigurable Computing;

November 1, 2005, IEEE Computer Society Educational Activities Board meeting, Philadelphia, USA, (ppt)
keynote address

Programmable SoC progress stalled by unqualified programmers: CS curriculum upgrades enforceable or EE task force needed?

 New EXploratory Technology (NEXT) Conference, Salo, Finland, October 3 - 4, 2005 (pps)

keynote

Reconfigurable Computing (RC) being Mainstream: Torpedoed by Education

2005 International Conference on  Microelectronic Systems Education (cfp),   12 - 13 June 2005, Anaheim, California,  co-located with DAC (Design Automation Conference) (DAC)  (ppt)

keynote

Supercomputing goes Reconfigurable - About key issues and their impact on CS education;

Winter  International Symposium on Information
and Communication Technologies (WISICT 2005), Cape Town, South Africa, January 3 - 6, 2005 (ppt)

2004:

invited presentation

Reconfigurable Technologies

Seminar at Department of Informatics  (Informatics), Kyushu University (Kyushu Univ), Higashi-ku, Fukuoka City, Kyushu, Japan; July 23, 2004,  (part 1 ppt)  (part 2 ppt) 

opening keynote address

Reconfigurable HPC: torpedoed by Deficits in Education ?

Workshop on Reconfigurable Systems for HPC (RHPC); July 21, 2004, to be held in conjunction with HPC Asia 2004, 7th International Conference on High Performance Computing and Grid in Asia Pacific Region,  July 20 - 22, 2004, Omiya Sonic City, Tokyo Area, Japan   (ppt)  (pdf)

keynote

The Changing Role of Computer Architecture Education within CS Curricula

Workshop on Computer Architecture Education (WCAE 2004) June 19, 2004, at 31st International Symposium on Computer Architecture (ISCA),  Munich, Germany, June 19-23, 2004   (ppt)  (pdf)


invited full day tutorial

Reconfigurable HPC;

Technical University of Talinn (TTU); May 7, 2004, Talinn, Estonia,    (ppt part 1)    (ppt part 2)    (ppt part 3)    (ppt part 4)


keynote address

Software or Configware? About the Digital Divide of Computing;

18th International Parallel and Distributed Processing Symposium (IPDPS),  April 26–April 30, 2004, Santa Fe, New Mexico,  Eldorado Hotel  (ppt)


invited presentation

The Digital Divide of Computing;

2004 ACM International Conference on Computing Frontiers (CF04); April, 14-18, 2004. Ischia, Italy,    (ppt  (pdf)


keynote address

The Impact of Morphware on Parallel Computing;

12-th Euromicro Conference on Parallel, Distributed and Network based Processing (PDP04); February, 11-13, 2004. A Coruña, Spain,    (ppt)


2003:


invited presentation:

Morphware: neue Perspektiven für eingebettete Systeme;

Selbstoptimierende Systeme des Maschinenbau: Workshop Selbstoptimierung und Adaption, Paderborn, Germany, 24. - 25. November 2003   (ppt)

Zusammenfassung:
Der Vortrag veranschaulicht fortgeschrittene Trends zum aktuellen neuen Paradigma der Mikroelektronik-Anwendung und deren technologische Grundlagen und gibt einen Ausblick auf deren Wirkung auf kommerzielle Infrastrukturen und die Lehrgebäude von Elektrotechnik und Informatik.




invited paper:

Data-Stream-Based Computing: Models and Architectural Resources;

International Conference on Microelectronics, Devices and Materials (MIDEM 2003), Ptuj, Slovenia, Oct.1-3, 2003

Abstract:
Embedded System Design often turns hardware / software co-design into hardware / configware / software co-design. The transition from HDL languages to sources of higher abstraction levels, like System-C and others, encourages to go from complex design flows to compilation techniques which are supported by a simple machine paradigm model. Because the instruction-stream-based von Neumann mind set does not support configware compilation we need a data-stream-based second model, which has been popularized recently by a number of projects in reconfigurable computing, and even for a hardwired solution. The paper introduces this anti machine model and its archtectural resources in detail.  -- ppt  --  pdf  --  fm




accepted paper  (together wirh: R. Jacobi, M. Ayala-Rincon, C. Llanos):

Using Rewriting-Logic Representation for Functional Verification in Data-Stream-Based Reconfigurable Computing

Forum on Specification and Design Languages (FDL'03), September 23 - 26, 2003 – Frankfurt, Germany - ppt - pdf



invited lectures:

Reconfigurable Computing and its Enabling Technologies -- for the Personal Supercomputer (PS) to replace the PC;

THALES internal workshop; September 18, 2003, Orsay, France    -    ppt




invited paper:

Toward Reconfigurable Computing via Concussive Paradigm Shifts;

Anniversary Colloquium at Prof. Glesner's 60th Birthday;  August 29, 2003, Darmstadt, Germany. - ppt  --  * --  pdf  --  fm

Abstract:
The paper is beginning with a survey on paradigm shifts affecting academic mind sets. Then the paper points out, how reconfigurable platforms and their applications introduce fundamental padadigm shifts colliding with the tradional backgrounds of EE and CS professionals. This has a heavy impact on several areas, such as design automation, embedded system design, parallel algorithms, compilation techniques, computing machine principles and architectures and other areas. Our academic education system is heading toward a desaster, where our graduates will not be sufficiently qualified to meet the requirements of the labour market. The paper discusses proposals to solve these problems.



invited lectures:

Reconfigurable Computing and its Compilation Techniques;

and

Distributed Memory and Datastream-based Reconfigurable Computing;

Summer School on "Multiprocessor Systems on Chip";  Örebro, Sweden, August 25-27, 2003; jointly organized by the Swedish National Program on Socware, the Strategic Integrated Electronic Systems Research Center at Linköping Universit, and the Competence Center for Circuit Design at Lund University.  - The main theme is to present fundamental issues related to the design
of multiprocessor SoCs. The main audience are the PhD students involved in these three programs. - part 1: ppt  part 2:  ppt



colloquium talk:

Reconfigurable Computing a la Mead and Conway;

Kolloquium, Informatik X: Rechnertechnik und Rechnerorganisation / Parallelrechnerarchitektur TU München;  August 21 2003, Munich, Germany. - ppt
 



invited lectures:

Reconfigurable Computing and its Impact on SoC and beyond;

REASON Summer School on FPGA-based and Reconfigurable Systems*, University of Ljubljana, Ljubljana, Slovenia, August 11-15 August 2003.  . - ppt



*) IST-2000-30193


opening keynote address:

A Mead-&-Conway-like Break-through is overdue;

Dagstuhl Seminar Nº 03301,  Dynamically Reconfigurable Architectures; Dagstuhl, Germany, 20. 07.-25. 07. 2003, 
Abstract (html) | presentation (ppt) | Dagstuhl fotos | program | fotos from Peter | fotos from Theo | e-mail newsgroup initiated at this seminar |


invited presentation:

Reconfigurable Computing and its Impact;

intel On Chip Reconfigurable Computing and Communication Workshop (intel ORCC workshop), Hillsboro, Oregon, USA, May 15-16, 2003 - ppt - - pps- - ppt_old_PowerPoint - - pps_old_PowerPoint



invited paper:

Datastream-based Reconfigurable Computing;

Dresdner Arbeitstagung Schaltungs- und Systementwurf (Workshop on Circuit and Systems Design - DASS´2003), in conjunction with  rhe Workshop System Design Automation (SDA´2003); Dresden, Germany, May, 8 - 9, 2003. . - ppt



invited opening keynote:

Are we ready for the Breakthrough ?;

10th Reconfigurable Architectures Workshop 2003 (RAW 2003), Nice, France, April 22, 2003, pdf | ppt


X
invited paper:

Data-Stream-based Computing and Morphware;

Joint 33rd Speedup and 19th PARS Workshop (Speedup / PARS 2003), Basel, Switzerland, March 19 - 21, 2003, pdf | ppt



table of contents of this page

2002:


invited presentation:

Data-stream-based Computing, Enabling Technology for Reconfigurable Computing; November 22, 2002, Seminar, EE department (ENE), University of Brasilia, Brasil, ppt



invited course on

Reconfigurable Systems; November 13, 14, 21, 2002, CS department, University of Brasilia, Brasil - for similar course viewgraphs see ENST, Paris,



invited position statement as a panelist :

Panel on Embedded Architectures: Configurable, Re-configurable, or what?  (Thursday, Oct 10, session 5, 4.00 - 5.00 p.m.)

Panelists: Pierre Paulin, STMicro (moderator), Henk Corporaal, IMEC, Reiner Hartenstein, Univ. Kaiserslautern,  Oz Levia, Improv Systems,  Marco Pavesi, Italtel, Chris Rowen, Tensilica.

CASES 2002 (International Conference on Compilers, Architecture, and Syntheses for Embedded Systems), October 8-11, 2002, Grenoble, France, co-located with EMSOFT 2002 (Oct 7-9)

ppt file of the position statement: pps | Ippt
.
use PowerPoint 2002 to avoid animation bugs
 --  download Windows 2002/XP viewer


invited presentation

Trends in Reconfigurable Logic and Reconfigurable Computing;

9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia - pdf- pps - ppt - for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk   --  download Windows PowerPoint 97 viewer         2002/XP viewer

Abstract:
The paper gices a survey on Reconfigurable Logic and Reconfigurable Computing, as well as
on recent R&D trends in these areas. The paper also points out the weak aspects of recent
developments and proposes new directions to go.


invited presentation (together wirh Michael Herz (Agilent Technologies), Miguel Miranda, Erik Brockmeyer (IMEC, Leuven, Belgium), Francky Catthoor (IMEC and K.U.Leuven, Belgium):

Memory Organisation for Stream-based Reconfigurable Computing;

9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia - pdf - pps-ppt - for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk   --  download Windows 2002/XP viewer

Abstract:
The paper gives a survey on methods to cope with the memory bandwidth problem, especially
in the context of data-stream-based computing systems, like reconfigurable (and hardwired)
data path arrays, introduced by the first paper of this session and elsewhere.


keynote address

Disruptive Trends by Custom Compute Engines.

The 12th International Conference on Field Programmable Logic and Application  FPL 2002, September 2 - 4, 2002,   La Grande-Motte (Montpellier, France)

Abstract: pdf  Presentation: ppt | pps   --  download Windows   PowerPoint 97 viewer         2002/XP viewer


keynote address

Reconfigurable Computing: urging a revision of basic CS curricula.

The 15th International Conference on Systems Engineering  - ICSENG02,  Las Vegas, USA, 6-8 August, 2002 - pdf - ppt | pps

Abstract
The paper introduces the coming dichotomy of computing sciences stimulated by the emerging methodology around  reconfigurable computing and its impact on the classical mindset of controlflow-driven computing. The paper also discusses this  new methodology as a challenge to computer science and engineering curricula.


invited presentation (in German language)

Data-Stream-based Computing: Antimaterie der Informatik
(Data-Stream-based Computing: Antimatter of Informatics)

60th semester anniversary workshop of the chair "Informatik I" (Prof. Reusch), University of Dortmund, July 18. - 19, 2002 --  ppt | pps
 --  download Windows 2002/XP viewer

Abstract
It is the mission of the talk to illustrate the emerging dichotomy of computing sciences. Taking current instruction-driven mainstream computing as the world of matter in informatics, the talk introduces the data-stream-based computing methodlolgy as its world of antimatter with an antimachine paradigm and other anti issues.


invited course

Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design

CNRS internal workshop, ENST, Paris, July 8 , 2002 -

prelininary versions of Powerpoint Files (will be updated after the course date): part 1, Reconfigurable Computing (RC):  ppt1  part 2, Data-Stream-based Computing:  ppt2  part 3, Resources for RC and Data-Stream-based Computing:  ppt3 part 4, Recent developments:  ppt4


keynote address

Stream-based Computing - Antimatter of Informatics;

First International Conf. on Intelligent Computing and Information Systems (ICICIS 2002), Cairo, Egypt, June 24-26, 2002. - pdf - pps  for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk

Abstract:
Recently the term "stream-based computing" has become more
popular. The paper illustrates, why stream-based computing
as the direct counterpart of von-Neumann-based concurrent
computing disrupts the fundamentals of computing science.


keynote address

Configware / Software Co-Design: Be Prepared For the Next Revolution!

The 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02), Brno, Czech Republic, April 17 - 19, 2002 - pdf - pps  for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk   --  download Windows 2002/XP viewer

Abstract.
Reconfigurable computing has proceeded from niche to mainstream. This is not new any more. But now the provocative mind set, hidden behind its methodology, is heading toward a fundamental EECS curricular revolution. The talk introduces the principles of this antimatter
of computing science. However,  in contrast to particle physics, merging matter and antimatter  does not lead to annihilation, but to synergies. This provides a promising alternative to hardware software so-design: configware / software co-design


.
table of contents of this page

2001:


invited* presentation:
.
Stream-based Arrays: Converging Design Flows for both, Reconfigurable and Hardwired .... ;
.

IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2001), December 2- 4, 2001,  Montpellier, France --  viewgraphs: (ppt)  --  download Windows  2002/XP viewer
*) scheduled late as a replacement of a no show


invited presentation:

Reconfigurable Computing
Architectures and Methodologies for System-on-Chip

3rd Workshop.on  Enabling Technologies for System-on-Chip Development 2001   _
November 19-20, 2001,  Tampere, Finland.      -   see the program

Abstract. Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA programming is RAM-based, but by structural programming (also called "(re)configuration") instead of  procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: ready for SoC design.

Now also accelerator definition may be -at least partly- conveyed from vendor site to customer site, such as e. g. for upgrades. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods, but not really compilation. Supporting only fine-grained reconfigurability of roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methods - similar to CAD  for hardwired logic.

From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging competitor to FPGAs.  In contrast to FPGAs, the Reconfigurable Computing scene uses arrays of coarse-grained  reconfigurable datapath units (rDPUs) with drastically reduced  reconfigurability overhead: to directly configure high level parallelism. But the classical machine paradigm does not support soft datapaths because “instruction fetch” is not done at run time.

To introduce the new business model to cope with the current accelerator design crisis a transition from CAD  to compilation is needed,  and from hardware/software co-design to configware/software co-compilation.  The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.

 
Enabling Technologies for System-on-Chip Development 2001
Enabling Technologies for System-on-Chip Development 2000
Enabling Technologies for System-on-Chip Development 1999

 

paper (pdf), viewgraphs (ppt) (pps*)
 download Windows  PowerPoint 97 viewer  2002/XP viewer
  for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk
____________
*) self-executing PowerPoint Show: push 
   right mouse button and  select "save link as"
.


keynotes

Enabling Technologies for Reconfigurable Computing

invited Post Conference Tutorial,  3rd Workshop.on 
Enabling Technologies for System-on-Chip Development 
November 21, Tampere, Finland

Part 1: Reconfigurable Computing (RC)  (pps*) (ppt)
Part 2: Compilation Techniques for RC   (pps*) (ppt)
Part 3: Resources for Stream-based RC (pps*) (ppt)
Part 4: Recent Trends, also on FPGAs    (pps*) (ppt)
  for pdf files use Acrobat Reader 5   --   pps files first download, then open from your harddisk
____________
*) self-executing PowerPoint Show: push 
   right mouse button and  select "save link as"
.

invited embedded tutorial:

SBCCI 2001 - 14th Symposium on Integrated Circuits  and Systems Design *
(together with: SBMICRO - 2001   Int'l Conf. on Microelectronics and Packaging
and: SBAC-PAD 2001   13th Symp. on Computer Architecture and High Performance Computing
Pirenopolis, DF, Brazil, September 10-15, 2001, Pireneus Pousada Hotel

"Reconfigurable Computing:
the Roadmap to a New Business Model
- and its Impact on SoC Design"

Abstract. Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. But after a decade of  research on Reconfigurable Computing a new breed of reconfigurable platforms is an emerging competitor to FPGAs: coarse grained reconfigurable platforms with drastically improved efficiency.

Like microprocessor usage, also programming reconfigurable platforms is RAM-based, but by structural programming instead of  procedural programming. But so far reconfigurable platforms do not yet repeat the RAM-based success story of the software industry. Because of lacking awareness of this paradigm switch there is not yet a configware industry. A new business model is needed, as well as a fundamentally new product design flow approach.

This embedded tutorial surveys a decade of R&D on Reconfigurable Computing and related CAD. The paper illustrates, that results are available for commercialization: to cope with the current SoC design crisis by a transisiton from hardware/software co-design to to platform-based SoC design by configware/software co-compilation. The paper shows a roadmap to the success story of a coming  configware industry.

(paper: pdf, viewgraphs: ppt, download Windows Powerpoint viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer


invited embedded tutorial (keynote):

DSD'2001 - EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN:
Architectures, Methods, and Tools, Warsaw, Poland, September 4 - 6, 2001.

Reconfigurable Computing: a New Business Model - and its Impact on SoC Design

Abstract. Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA application is RAM-based, but by structural programming (also called "(re)configuration") instead of  procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design.

Now also accelerator definition may be -at least partly- conveyed from vendor site to customer site. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods.

From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging future competitor to FPGAs.  Supporting roughly single bit wide configurable logic blocks (CLBs) the  mapping tools are mainly based on gate level methods - similar to CAD  for hardwired logic. In contrast to this fine-grained reconfigurability,  the Reconfigurable Computing scene uses arrays of coarse-grained  reconfigurable datapath units (rDPUs) with drasticallyreduced  reconfigurability overhead: to directly configure high level parallelism.

But the “von Neumann” paradigm does not support soft datapaths because “instruction fetch” is not done at run time, and, since most reconfigurable computing arrays do not run parallel processes, but multiple pipe networks  instead. To introduce the new business model to cope with the current accelerator design crisis a transition from CAD to compilation is needed,  and from hardware/software co-design to configware/software co-compilation.  The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.

(paper: pdf, viewgraphs: ppt, download Windows Powerpoint viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer



invited statement as a panelist:
together with Lech Józwiak (chair), Steve Guccione (Xilinx), Rolf Ernst (TU Braunschweig), Kjell Torkelsson (Ericsson), Adam Postula (U Queensland): Reconfigurable Computing; - September 5,  14.00 - 15.30 hrs

DSD'2001 - EUROMICRO Symposium on Digital System Design:
Architectures, Methods, and Tools, Warsaw, Poland, September 4 - 6, 2001.


invited* embedded tutorial:

DATE 2001 -  Design, Automation and Test in Europe, Conference & Exhibition
13-16 March, 2001. ICM/Neue Messe, Munich, Germany

A Decade of Reconfigurable Computing:
A Visionary Retrospective [p. 642]

Abstract: The paper surveys a decade of R&D on coarse grain  reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of  computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.

(slides: ppt, paper: pdf, download Windows PowerPoint viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer



*) by program committee turned from submission into double length embedded tutorial

invited embedded tutorial:

Coarse Grain Reconfigurable Architecture

ASP-DAC 2001 - Asia and South Pacific Design Automation  Conference 2001
January 30 - February 2, 2001, Conference Center, Pacifico Yokohama, Yokohama, Japan

Abstract. The paper gives a brief survey over a decade of R&D on coarse grain reconfigurable hardware and related compilation techniques and points out its significance to the emerging discipline of reconfigurable computing.

(slides: ppt, paper:  pdf, download Windows PowerPoint  viewer)  for pdf files use Acrobat Reader 5   --  download Windows   PowerPoint 97 viewer         2002/XP viewer

keynotes


2000 and earlier
(a selection)

invited paper:

The Microprocessor is no more General Purpose: why Future Reconfigurable Platforms will win; Proceedings of the International Conference on Innovative Systems in Silicon, ISIS'97, Austin, Texas, USA, October 8-10, 1997  - pdf - html    Honorable Mention* by    E-mail


*) post conference replacement of a best presentation award (not yet established at ISIS before 1997)

invited course:

Reiner Hartenstein (invited tutorial, together with Jürgen Becker): Xputers and Their Programming Environment; ARM Advanced RISC Machines, Ltd. Europe, Cambridge, UK, July 24, 1996.

Abstract: Not running any instruction streams the Anti-Machine or Xputer is the counterpart of von Neumann by using data counters instead of a programm counter;


invited course:

Reiner Hartenstein (invited full day VLSI Design Course; together with R. Kress, W. Reinig):: Xputers: Principles, Architectures, Performance; Tutorial on Xputers; LIRMM, University of Montpellier, Montpellier, France, Sept. 1995

Abstract: Not running any instruction streams the Anti-Machine or Xputer is the counterpart of von Neumann by using data counters instead of a programm counter To cope with the von Neumann Syndrome we need the alternative Anti Machine paradigm also called Xputer;


(with A.Hirschbiel, M. Riedmueller, K. Schmidt, M.Weber):

A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24, Hawaii Int'l. Conference on System Sciences, Koloa, Hawaii, 1991 pdf  -

Second Best Paper Award (Honorable Mention) -Speaker: R. Hartenstein



invited reprint (with A. Hirschbiel, K. Schmidt, M. Weber):

A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Future Generation Computer Systems 7 91/92, p. 181-198, North  Holland Purlishing Co. Amsterdam / New York;

Invited reprint from Proc. InfoJapan'90- (Int'l Conf. memorating the 30th Anniversary of the Computer Society of Japan), Tokyo, Japan, 1990



invitedreprint (with M. Riedmuller, K. Schmitt, M. Weber):

A Novel Asic Design Approach Based on a New Machine Paradigm; IEEE Journal of Solid State Circuits, July 1991 - ps -

Invited reprint of a paper from from Proc. ESSCIRC 1990, Geneva, Switzerland




(with A.Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber):

Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Preprocessing; 12th DAGM-Symposium Mustererkennung (Pattern Recognition), Oberkochen-Aalen, Germany, 1990  -- html  -

Best Paper and Best Presentation Award (DM 1000.--) Speaker: Michael Weber


  keynotes         for more papers see here


Ph. D. theses available:


Ulrich Nageldinger
: Coarse-grained Reconfigurable Architectures Design Space Exploration; Dissertation, 2001 -  pdf


Michael Herz
: High Performance Memory Communication Architectures for Coarse-grained Reconfigurable Computing Systems; Dissertation 2001, Kaiserslautern University of Technology -  pdf  html


Juergen Becker
: A Partitioning Compiler for Computers with Xputer-based Accelerators, Ph. D. Dissertation 1997, Kaiserslautern University of Technology  - URL - pdf


Rainer Kress
: A Fast Reconfigurable ALU for Xputers, Ph. D. Dissertation 1996, Kaiserslautern University of Technology 
- not available in electronic form, but you may request the printed version -- 

Remarks on the Supersystolic Array (Super systolic array): [ Google | Google2 | Wiki ]

This thesis by Rainer Kress  introduces the supersystolic array - the generalization of the systolic array. See Preface: [ html | pdf  ]  


Karin Schmidt: A Program Partitioning, Restructuring, and Mapping Method for Xputers, Ph. D. Dissertation 1994, Kaiserslautern University of Technology  - available from publisher Shaker Verlag, ISBN: 3-8265-0495-X


Alexander Hirschbiel: A Novel Processor Architecture  Based on Auto DataSequencing and Low Level Parallelism;  Ph. D. Dissertation, March 1, 1991, Kaiserslautern University of Technology (available only on paper as a brochure; you may request it - but we might charge you for the xeroxing cost)

Remarks on the Generic Address Generator (GAG): [ google | Wiki ]

The methodology and the principles of the GAG have been described by Alexander Hirschbiel within this Ph. D. thesis by the following sections:
5.3.1 Data Sequencer of the MoM-2
5.3.1.1 Generation of Scan Loops
5.3.1.2 Compound Scan Tasks and Data-driven Scans
5.3.1.3 Proposal of Scan Macros
5.3.1.4 Design Alternative: Data Sequencing using an Escape Cache
5.3.1.5 Design Alternative: A less Autonomous Data Sequencer

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