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Workshop's poster

Report from the

1st BENEFIT

Workshop

on

Design Methodologies for Microelectronics

hold in

Smolenice, 11-13 Sept. 1995

BENEFIT COPERNICUS 94:0536

accompanied by Special Days

on European co-operation in research- 14 Sept. 1995

and

Industrial co-operation -Vienna Univ. of Technology, 15 Sept. 1995


Press conference "after" | Mentor Graphics' success: 1-2 | Slovak press: 1-2 | Concert in Dolna Krupa


ABOUT THE EVENT

OBJECTIVES
The first major event of the BENEFIT Concerted Action (CA0536), the action launched by the CEC within the framework of the COPERNICUS 94 programme, has been organised by the Institute of Computer Systems of the Slovak Academy of Sciences, the Faculty of Electrical Engineering and Information Technology of the Slovak Technical University (Bratislava, Slovakia), BIT - Bureau for International Research and Technology Co-operation Vienna and the Institute for Computer Technology of the Vienna University of Technology (Vienna, Austria) in co-operation with IEEE - Section Czechoslovakia, IEE - Section Slovakia, EUROMICRO, IFIP, Czech Technical University and Austria Computer Society. The main sponsor was the COMMISION OF THE EUROPEAN COMMUNITIES, Directorate Generale III for Science and Technology Co-operation.

The long-term goal of BENEFIT is to build a firm basis for scientific and technical collaboration among research groups from the Central and East European (CEE) countries and those from the European Communities within microelectronics and signal processing.

PROCEEDINGS
All accepted submitted papers, posters and invited papers were included and published in the proceedings. The proceedings were distributed at the Workshop. For an additional copy contact Elena Gramatova

WORKSHOP COMMITTEES

GENERAL CHAIR
Adam Pawlak
ARTEMIS/IMAG
Grenoble, France
PROGRAMME COMMITTEE
Michal Servit
Czech Technical University
Prague, Czech Republic
WORKSHOP PROGRAMME CHAIR
Raul Camposano, Synopsys, USA
Ed Cerny, Montreal University, Canada
Jan Chojcan, Silesian Technical University, Poland
Bernard Courtois, INPG/TIMA, France
Patrick Dewilde, Delft University, The Netherlads
Norbert Fristacky, Slovak Technical University, Slovakia
Manfred Glesner, Darmstadt University, Germany
Tadeusz Grabowiecki, Silesian Technical University, Poland
Reiner Hartenstein, Kaiserslautern University, Germany,
Manfred Horvat, BIT, Austria
Kurt Judmann, Technical University of Vienna, Austria
Valery Mikhov, Operating Systems Institute, Russia
Wolfgang Nebel, University Oldenburg, Germany
Antonio Nunez, University Las Palmas, Spain
Serafin Olcoz, TGI, Spain
Adam Pawlak, ARTEMIS/IMAG, France
Ivan Plander, Institute of Computer Systems, Slovakia
Wolfgang Rosenstiel, Tuebingen University, Germany
Mariagiovanna Sami, Politecnico di Milano, Italy
Michal Servit, Czech Technical University, Czech Republic
Andrzej Strojwas, CMU, USA
Ferenc Vajda, KFKI Research Institute for Measurement and Computing,, Hungary
CO-OPERATION DAY PROGRAMME CHAIR
Manfred Horvat
BIT, Vienna, Austria

INDUSTRIAL DAY PROGRAMME CHAIR

Kurt Judmann
Vienna University of Technology,Vienna, Austria

ORGANISING COMMITTEE and Organizing Team 
Elena Gramatova, Institute of Computer Systems, Bratislava, Slovakia
Karol Kosuk, Institute of Computer Systems, Bratislava, Slovakia
Bedrich Weber, Slovak Technical University, Bratislava, Slovakia
Peter Dekys, Slovak Technical University, Bratislava, Slovakia
CONTACT ADDRESS
Maria Fischerova
Institute of Computer Systems
Dubravska cesta 9 phone: +42 7 371 008
842 37 Bratislava fax: +42 7 371 004
Slovakia e-mail: DMM-95@savba.savba.sk
BENEFIT CO-ORDINATORS
Tadeusz Grabowiecki
STU-Gliwice
Gliwice, Poland

Roland Pleger
DLR, Project Management Division
Cologne, Germany 


WORKSHOP PROGRAMME

SUNDAY, SEPTEMBER 10, 1995

16.00-22.00 Registration 
 

MONDAY, SEPTEMBER 11, 1995

8.00-9.30 Registration

9.30 OPENING SESSION WELCOME and OBJECTIVES of the Event

10.00 CUSTOM COMPUTING MACHINES Room A
R.Hartenstein; Univ. Kaiserslautern, Germany
(invited speaker)

11.00-11.30 Coffee break

SESSION 1: HIGH LEVEL SYNTHESIS I Room A
Chair: N.Fristacky, STU Bratislava, Slovakia

1.1 OPTIMIZATION OF INTERCONNECTION BY INSTANCE RE-ASSIGNMENT
P.Pokorny, B.Vanthournout, I.Bolsens, H.De Man; IMEC, Leuven,
Belgium

1.2 TIMING DIAGRAMS AS A SPECIFICATION LANGUAGE FOR INTERFACE
CIRCUITS
W.Grass, Ch.Grobe, S.Lenk, W.D.Tiedeman; Univ. Passau, Germany

12.30-14.00 Lunch
 
 

SESSION 2A: HIGH LEVEL SYNTHESIS II Room A
Chair: V.Mikhov, Institute of Operating Systems, Moscow, Russia

2.1 PIPELINED SYSTEM DESIGN THROUGH SIMULATED ANNEALING
M.Coli, P.Palazzari; Univ. Roma, Italy

2.2 AHILES: PERFORMANCE DRIVEN HIGH LEVEL SYNTHESIS FROM VHDL
DESCRIPTION
A.Prihozhy, A.Smolsky; Acad. of Sci., Minsk, Belarus

2.3 MAPPING TOOLS FOR HIGH PERFORMANCE COMPUTING
L.Hluchy, D.Dobrovodsky, M.Dobrudsky; Acad. of Sci., Bratislava, Slovakia

ASSOCIATED POSTER BRIEF PRESENTATIONS:

P1 LIBRARY MODULES FOR REGULAR ARRAY DESIGN
T.Plaks; Univ. Gotheburg, Sweden

P2 A SUPPORT TOOL TO OBTAIN BETTER AND FASTER SYNTHESIS RESULTS
M.Mastretti, M.L.Busi, R.Sarvello; ITALTEL, Milano, Italy

P3 FROM HIGH-LEVEL SPECIFICATION TO LAYOUT - A CASE STUDY
V.Salapura, H.Gruenbacher, H.Gschwind; TU Vienna, Austria

P4 EXPERIENCES IN SCHEDULING OF DESIGN DECISIONS
R.Rauscher; Univ. Hamburg, Germany
 
 

SESSION 2B: APPLICATIONS Room B
Chair: R.Hartenstein, Univ. Kaiserslautern, Germany

2.4 A COMPARATIVE STUDY OF HIGH SPEED CIRCUIT DESIGN STYLES FOR SYSTOLIC ARRAYS
A.Bussell, S.Jones; Univ. Loughborough, United Kingdom

2.5 DESIGN OF A HIGH-PERFORMANCE DES ENCRYPTION ENGINE
T.Volfschutz, P.Slaba; CTU Prague, Czech Republic

2.6 IMPLEMENTATION OF A GENERAL-PURPOSE PROCESSOR MACRO
F.Drapal, J.Danecek, A.Pluhacek, M.Z.Servit; CTU Prague, Czech Republic

ASSOCIATED POSTER BRIEF PRESENTATIONS:

P5 NEURAL NETWORK BASED ON VLSI PROCESSING MEMORY
V.V.Barinov, G.R.Kane, T.Y.Krupkina; MIET, Moscow, Russia

P6 THE DESIGN OF NON CONTACTING HUMAN TREMOR SENSOR (NHTS) BASED DIAGNOSIS SUPPORT SYSTEM
H.Manhaeve, J.Vanneuville, A.Sinnaeve; KIHWV, Oostende,
Belgium

P7 DESIGN OF DSP CHIP USING HIGH LEVEL SYNTHESIS APPROACH
J.Uhrin, EDC, Leuven, Belgium

15.45-16.15 Coffee break
 

SESSION 3: MODELLING Room A
Chair: A.Pawlak, Artemis/IMAG, Grenoble, France

3.1 GATE-LEVEL POWER ESTIMATION USING TRANSIENT ANALYSIS
J.Zejda, E.Cerny, S.Shenoy, N.C.Rumin; Univ. Montreal, Canada

3.2 METHODS FOR DESCRIBING BEHAVIOUR OF NONELECTRICAL COMPONENTS
FOR SIMULATION OF CIRCUITS AND SYSTEMS
P.Schneider, S.Wuensche, P.Schwarz; Fraunhofer Inst., Dresden, Germany

3.3 THE INTERLEAVED METHOD FOR EFFICIENT EXECUTION OF CHDL SIMULATION PROGRAMS
M.Thor; Acad. of Sci., Warsaw, Poland

ASSOCIATED POSTER BRIEF PRESENTATIONS:

P8 THE METHODS AND ALGORITHMS OF ANALYSIS FOR PARAMETRIC CIRCUITS
V.N.Lantsov, A.G.Dolinin, M.B.Komarov, A.S.Merkutov; Univ. Vladimir, Russia

P9 TEST MODELLING OF MIXED SIGNAL DEVICES
J.Povazanec, G.E.Taylor; Univ. Leeds, United Kingdom

P10 A NONMONOTONIC GENERATOR OF VHDL MODELS SATISFYING VITAL REQUIREMENTS
A.Pulka; TU Gliwice, Poland

19.00 Welcome party
 
 

TUESDAY, SEPTEMBER 12, 1995

9.00 INDUSTRIAL HARDWARE/SOTFWARE CO-DESIGN Room A
K.Buchenrieder; Siemens, Germany
(invited speaker)
 

10.00-10.30 Coffee break
 

SESSION 4: HARDWARE/SOFTWARE CO-DESIGN I Room A
Chair: E.Cerny, Univ. Montreal, Canada

4.1 A TWO-LEVEL HARDWARE/SOFTWARE CO-DESIGN FRAMEWORK FOR AUTOMATIC ACCELERATOR GENERATION
R.W.Hartenstein, J.Becker, R.Kress, H.Reinig, K.Schmidt;
Univ. Kaiserslautern, Germany

4.2 INCREMENTAL HARDWARE ADDRESS GENERATION
M.Kaspar, P.Schaumont, I.Bolsens, H.De Man; IMEC, Leuven,
Belgium

4.3 A DESIGN EXAMPLE USING CASTLE
P.G.Ploger, J.Wilberg; GMD, Birlinghoven, Germany

12.00 POSTER SESSION I Room C

13.00-14.30 Lunch
 
 

SESSION 5A: HARDWARE/SOFTWARE CO-DESIGN II Room A
Chair: M.Servit, CTU Prague, Czech Republic

5.1 NOVEL SEQUENCER HARDWARE FOR HIGH-SPEED SIGNAL PROCESSING
R.W.Hartenstein, H.Reinig; Univ. Kaiserslautern, Germany

5.2 OPTIMAL TASK MAPPING IN A HARDWARE/SOFTWARE CO-DESIGN ENVIRONMENT
A.Bender; Univ. Passau, Germany

5.3 AN ADAPTIVE STRATEGY IN HARDWARE-SOFTWARE CO-DESIGN FOR REAL-TIME EMBEDDED SYSTEMS
V.Toporkov; Univ. Moscow, Russia
 

ASSOCIATED POSTER BRIEF PRESENTATION:

P11 A HARDWARE-SOFTWARE CO-DESIGN METHODOLOGY BASED ON FORMAL SPECIFICATION AND HIGH-LEVEL ESTIMATION
C.Carreras, J.C.Lopez, M.L.Lopez, C.Deldago-Kloos;
Univ. Madrid, Spain
 
 

SESSION 5B: ARTIFICIAL INTELLIGENCE TECHNIQUES IN DESIGN Room B
Chair: T.Grabowiecki, TU Gliwice, Poland

5.4 HEURISTIC ALGORITHMS FOR MINIMAL INPUT SUPPORT PROBLEM
L.Jozwiak, P.A.Konieczny; TU Eindhoven, The Netherlands

5.5 KNOWLEDGE-BASED CONFIGURATION DESIGN OF ELECTRONIC DEVICES: A CASE STUDY
A.V.Smirnov, A.S.Kulinitch, L.B.Sheremetov, P.A.Turbin; Acad. of Sci., St. Petersburg, Russia

ASSOCIATED POSTER BRIEF PRESENTATIONS

P12 GENETIC ALGORITHM IN THE DESIGN OF MULTIPLIER-FREE DIGITAL FILTERS
R.Cemes, D.Ait-Boudaoud; Univ. Bournemouth, UK

P13 GENETIC ALGORITHMS FOR ANALOG CIRCUIT DESIGN
B.Nowak; TU Gliwice, Poland

P14 GENETIC ALGORITHMS IN TEST GENERATION ON REGISTER TRANSFER LEVEL
J.Stefanovic, E.Gramatova; STU Bratislava, Slovakia

16.00-16.30 Coffee break

16.30 VENDOR SESSION Room A

19.00 Dinner
 

WEDNESDAY, SEPTEMBER 13, 1995

9.00 CAUSALITY AND COMPATIBILITY VERIFICATION OF REAL-TIME INTERFACE SPECIFICATIONS
E.Cerny, K.Khordoc; Univ. Montreal, Canada
(invited speakers)
 

10.00-10.30 Coffee break
 
 

SESSION 6A: FIELD PROGRAMMABLE LOGIC Room A
Chair: M.Glesner, Univ. Darmstadt, Germany

6.1 KEY ISSUES FOR FPGA DESIGN TOOLS
A.Ditzinger; ISDATA, Karlsruhe, Germany

6.2 MULTILEVEL DECOMPOSITION METHOD AND ITS APPLICATIONS
IN FPGA-BASED SYNTHESIS
T.Luba, P.Godlewski; TU Warsaw, Poland

6.3 FLEXIBLE MODULE GENERATORS FOR COMPLEX ARRAY-BASED PLDs
H.-J.Brand, F.Dresig, R.List; TU Chemnitz, Germany

6.4 RECONFIGURABLE FPGAs DUAL ROLE: IN-SYSTEM TEST AND SYSTEM LEVEL LOGIC
J.Rosenberg; ATMEL, San Jose, USA

ASSOCIATED POSTER BRIEF PRESENTATIONS:

P15 DECOMPOSITION TECHNIQUES FOR LOOK-UP TABLE BASED FPGA DESIGN
V.Dvorak; Univ. Brno, Czech Republic

P16 FPGA-INTERFACES FOR AN EXPERIMENTAL NETWORK
F.Pucher; Univ. Gratz, Austria

P17 FAST RESIDUAL ARITHMETIC WITH FPGAs
M.Sprachmann, V.Hamann; TU Vienna, Austria
 

SESSION 6B: DESIGN FOR TESTABILITY Room B
Chair: R.Ubar, TU Tallinn, Estonia

6.5 CIRCULAR SELF-TEST PATH AS A UNIVERSAL BIST TECHNIQUE
A.Krasniewski; TU Warsaw, Poland

6.6 RT LEVEL TEST SCHEDULING PROCEDURE
J.Hlavicka, P.Kotasek, Z.Kotasek; CTU Prague, Czech Republic

6.7 REVIEW OF CURRENT TESTING METHODS FOR ANALOGUE CIRCUITS
V. Kolarik; Univ. Brno, Czech Republic

ASSOCIATED POSTER BRIEF PRESENTATIONS

P18 ATPG SYSTEM FOR HIGHLY SEQUENTIAL CIRCUITS USING DFT TECHNIQUES
M.A.Allende, F.J.Llacer, M.Martinez, S.Bracho, Univ. Cantabria, Santander, Spain

P19 A TESTABILITY IMPROVEMENT METHOD BASED ON VHDL DESCRIPTION AND HIGH LEVEL SYNTHESIS
R. Baraniecki, A.T. Rosinski; Acad. of Sci., Poland

P20 A NEW APPROACH TO DESIGN OF MULTIFAULT-IRREDUNDANT CIRCUITS BY ALGEBRAIC TRANSFORMATIONS
E. Goldberg, Y. Novikov; Acad. of Sci., Minsk, Belarus

P21 VLSI SYSTEM TEST DESIGN: EXPERIENCE AND SOME RESULTS IN
MICROPROCESSOR FUNCTIONAL TEST DESIGN WITH EFFECTIVE TOOL-AFTG
J. Hudec; STU Bratislava, Slovakia

P22 FAST GRADING OF DELAY FAULTS
A. Krasniewski, L.B. Wronski; TU Warsaw, Poland

P23 PSEUDOEXHAUSTIVE TEST SETS GENERATED BY CODE MATRIX BIT INVERSIONS
N. Novak; Univ. Liberec, Czech Republic

12.30-14.00 Lunch
 

SESSION 7: FORMAL VERIFICATION & TRANSFORMATIONAL DESIGN Room A
Chair: J. Hlavicka, CTU Prague, Czech Republic

7.1 TRANSFORMATIONS FOR THE DESIGN OF CONTROL PATH ARCHITECTURES
A.J.W.M.Berg, T.Krol; Univ. Twente, The Netherlands

7.2 TRANSFORMATIONAL DESIGN OF DIGITAL SYSTEMS RELATED TO GRAPH REWRITING
C.Huijs; Univ. Twente, The Netherlands

7.3 AN ALGORITHM FOR TIMING CONSISTENCY VERIFICATION
R.Bartos, N.Fristacky; STU Bratislava, Slovakia

7.4 FORMAL VERIFICATION OF A SIGNAL FLOW GRAPH
M.Cupak, M.Genoe, I.Bolsens; IMEC, Leuven, Belgium

ASSOCIATED POSTER BRIEF PRESENTATIONS:

P24 FULL-CHIP MASK LAYOUT DECOMPOSITION FOR TECHNOLOGY MIGRATION
Z.V.Apanovich, A.V.Klekovkin, A.G.Marchuk; Acad. of Sci., Novosibirsk, Russia

P25 FORMAL PROOF IN AN INDUSTRIAL ENVIRONMENT
C.Fleurey; IBM France

P26 DESIGN PORTABILITY
V.Tchoumatchenko, T.Vassileva; Univ. Sofia, Bulgaria

16.15-16.45 Coffee break

16.45 POSTER SESSION II Room C
 

CLOSING SESSION

Adam Pawlak and Michal Servit thank organizers from Academy of Sciences, i.e. Elena Gramatova's team and the Smolenice castle hosts . The whole team from Bratislava has worked very hard and fruitfully. Maria Fischerova deserves however, especially cordial THANKS.

19.00 Banquet with cultural programme 
 

SPECIAL DAY ON PAN-EUROPEAN CO-OPERATION

Smolenice castle, Slovakia
THURSDAY, SEPTEMBER 14, 1995

VIENNA INDUSTRIAL DAY

University of Technology, Vienna, Gusshausstrasse 27-29, Austria Lecture Hall: EI 8
FRIDAY, SEPTEMBER 15, 1995 

PRESENTATIONS

26 posters were exhibited during the workshop. All poster authors had 4 minutes for brief announcement of their work (2 transparencies were allowed) at the end of related session. Detailed presentations were done during Poster Sessions.
VENDOR PRESENTATIONS
Sagantec and Mentor Graphics has done demonstrations of their tools. Later, Mentor reported on the successes in Slovak Republic. 

ACCOMODATION

Accommodation was provided at the historical Smolenice castle and at the Dolna Krupa mansion

TRAVEL INFORMATION

HOW TO GET TO BRATISLAVA
By Plane: The nearest airports are in Bratislava and in Vienna (Vienna airport is about 40 kilometers from Bratislava). There is a bus line from the Vienna airport to the Bratislava Bus Station Mlynske Nivy approximately every two hours.

By Train: Bratislava Main Railway Station can be reached directly from Berlin, Budapest, Prague, Vienna, Warsaw and Moscow.