(k)Publications

by

Reiner Hartenstein

Legend:

.	class of paper
a	abstract
ai	invited abstract
B	books
bj	sollicited contributions to journals and books
gj	refereed contributions to journals and books
b	sollicited
g	refereed
n	not refereed
p	popular
i	reports, internal reports, lecture notes etc.
k	invited or keynotes (not refereed)
kj	invited contributions to journals and books
s	submitted
w	web-based newsletter
wi	invited for web-based newsletter

(Translation of non-English titles into English: see Appendix)


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(gj) Ein elektronischer Zufallszahlengeber; Elektronik 10, 1961 - translation of title -
(gj) (zus. mit K.-H. Zörner) Der 'Servo-Zähler', ein Analog-Digital-Wandler; ATM Archiv für Technisches Messen, August 1963 - translation of title -
(i) (zus. mit U. Jochimsen) Steuergerät zur Datenausgabe auf Lochstreifen durch ein- oder zweidimensional origaniserte Abfrage von Datenquellen; KFK 201, Kernforschungszentrum Karlsruhe, Januar 1964 - translation of title -
(i) Modifiziertes Steuergerät zur Datenausgabe auf Lochstreifen mittels Tally-Locher 420 PR; KFK 245, Kernforschungszentrum Karlsruhe, August 1964 - translation of title -
(i) (zus. mit W. Jüngst) Ein flexibles elektronisches Bausteinsystem zur Datenerfassung bei kernphysikalischen Experimenten; KFK 275, Kernforschungszentrum Karlsruhe, Dezember 1964 - translation of title -
(i) (zus. mit P. Gruber) Ein modifiziertes Steuergerät zur Datenausgabe auf Streifenlocher Tally 420 PR und elektronischer Schreibmaschine IBM 73/BCD; KFK 316, Kernforschungszentrum Karlsruhe, März 1965 - translation of title -
(i) Das PATTERN-HANDLING-Software-Paket; int. Bericht, Forschungsgruppe automatische Zeichenerkennung, Institut für Nachrichtenverarbeitung, Universität Karlsruhe 1967 - translation of title -
(i) (zus. mit H. Kazmierczak und F. Holdermann) Automatischer Klassifikator-Entwurf; in: Jahresbericht des Instituts für Nachrichtenverarbeitung, Universität Karlsruhe 1967 - translation of title -
(b) (zus. mit F. Holdermann und H. Kazmierczak) Verarbeitung, Erzeugung und Erkennung von Zeichenmustern; in: Nichtnumerische Informationsverarbeitung (Hrsg.: R. Gunzenhäuser), Springer-Verlag, Wien / New York, 1968 - translation of title -
(i) Anwendung abstrakter Automaten in der Zeichenerkennung; in: Jahresbericht 1968 des Instituts für Nachrichtenverarbeitung, Uni. Karlsruhe, 1968 - translation of title -
(i) Entwurf abstrakter Automaten aus regulären Ausdrücken und deren Anwendung auf die Zeichenerkennung; Vortragsmanuskript, vervielfältigt, Seminar am Institut für Nachrichtenverarbeitung, Univ. Karlsruhe, 1968 - translation of title -
(g) Über die Anwendung des endlichen Akzeptors auf das Zeichenerkennungsproblem; Dissertation, Universität Karlsruhe, 1969 - translation of title -
(i) Synthese endlicher Automaten zur Musterklassifikation und Musterverarbeitung; Kap. im Forschungsbericht Automatische Bildauswertung und Zeichenerkennung (Hrsg.: H. Kazmierczak), Univ. Karlsruhe, 1969 - translation of title -
(g) Suchlistenstruktur zur Darstellung gerichteter Graphen und deren Anwendung bei Synthese und Minimierung spezieller endlicher Automaten; Elektronische Rechenanlagen, H. 4, 1970 - translation of title -
(i) Über den Entwurf endlicher Automaten; in: Jahresbericht 1970 des Instituts für Nachrichtenverarbeitung, Universität Karlsruhe, 1970 - translation of title -
(gj) Synthese endlicher Automaten bei Problemen der Erkennung, Klassifikation und Informationsreduktion; Elektronische Informationsverarbeitung und Kybernetik, EIK 7, Heft 5/6, 1971 - translation of title -
(i) Grundlagen zum Versuch 'Rückgekoppelte Schaltnetze'; Kapitel zum Skriptum des Praktikums Technische Informatik, Informatik IV, Univ. Karlsruhe, 1971 - translation of title -
(i) Logik-Testautomaten, interner Bericht, Informatik IV, Univ, Karlsruhe, 1971 - translation of title -
(i) Grundlagen zum Versuch ´Mikroprogrammierung´; Kapitel zum Skript des Praktikums Technische Informatik, Inst. f. Informatik IV, Univ. Karlsruhe 1971 - translation of title -
(bj,p) (zus. mit K. Steinbuch) Zukunftsaspekte der Informationstechnik; in: Techniken der Zukunft, Bd. 1, Januar 1971 - translation of title -
(b,p) Wenn die Datenbank kommt; DIE WELT, 19. 6. 1971 - translation of title -
(b,p) (zus. mit K. Steinbuch) Information - gestern, heute, morgen; Messe-Magazin (Rank Xerox), April 1971 - translation of title -
(bj,p) Management-Information mit Computer und Bildschirm; Techniken der Zukunft 2, Juni 1971 - translation of title -
(b,p) (m. K. Steinbuch) Die vierte industrielle Revolution; Rank Xerox Magazin 1 / 1971 - translation of title -
(b,p) (zus. mit K. Steinbuch) Die vierte industrielle Revolution; Techniken der Zukunft 3, Nov. 1971 - translation of title -
(i) Konzept eines Hardware-Praktikums für Fortgeschrittene; internes Arbeitspapier, Institut für Informatik IV, Universität Karlsruhe, 1972 - translation of title -
(i) Grundlagen-Skriptum und Anleitungen zum Praktikum ´Technische Informatik´; Institut für Informatik IV, Universität Karlsruhe, 1972 - translation of title -
(gj) Elemente der Prüftechnik für digitale Schaltungen; Elektronik 22/4, 1973 - translation of title -
(i) Rechnerarchitektur und Mikroprogrammierung; Skriptum zur eigenen Vorlesung, Universität Karlsruhe, 1973 - translation of title -
(b) (zus. mit K.-D. Müller-Glaser) A Microprogrammable Display Processor Concept; in: (Ed.: L. Jones) Conference record of the 6th annual Workshop on Microprogramming, College Park, Maryland, ACM, New York 1973
(n) (zus. mit K.-D. Müller-Glaser) A Microprogrammable Display Processor for 3-dimensional Interactive Computergraphics; SIGMICRO Newsletter 4,2, 1973
(bj) dto., nachgedruckt in Computer Graphics, vol. 4, no. 2, 1973
(n) A Halfbaked Idea on a set of Register Transfer Primitives; SIGMICRO Newsletter vol. 4, no. 3, 1973
(n) Towards a Language for the Description of IC Chips; SIGMICRO Newsl.4,4, 1973
(g) Experimentiersystem für ein technisches Informatikpraktikum; in: (Hrsg.: P. Deussen) 2. Jahrestagung der Ges. für Informatik in Karlsruhe, Okt. 1972, Springer-Verlag Berlin/Heidelberg/New York 1973 - translation of title -
(g) Hierarchy of Interpreters for Modelling Complex Digital Systems; in: (Hrsg.: W. Brauer) 3. Jahrestagung der Ges. für Informatik in Hamburg, Okt. 1973, Springer-Verlag Berlin/Heidelberg/New York, 1973
(g) Increasing Hardware Complexity - A Challenge to Computer Architecture Education; in: (Eds.: G. J. Lipovski, S. Szygenda) Proc. of the First Annual Symposium on Computer Architecture, Gainesville, FL, Dec. 1973, ACM, New York, 1973
(n) Hierarchy of Levels within Computer Architecture; CAN - Computer Architecture News, vol. 3, Nr. 1, März 1974
(b) On the interpretive Mechanism in microprogrammed Systems; EUROMICRO journal 2, Oct. 1974
(g) Konzepte der Mikroprogrammierung; in: (Hrsg.: H.-O. Leilich) Preprints zur GI/NTG-Fachtagung Struktur und Betrieb von Rechnersystemen, Braunschweig, März 1974, Springer-Verlag Berlin/Heidelberg/New York 1974 - translation of title -
(b) Microprogramming Concepts - a step towards Structured Hardware Design; in: Preprints of the 7th Annual Workshop on Microprogramming, Palo Alto, Cal., Sept. 1974
(bj) (zus. mit Y. Chu et al.) Why do we need Hardware Description Languages; COMPUTER, Dec. 1974
(i) Introduction to formal descriptions in Computer Organisation; internes Arbeitspapier, Universität Karlsruhe, 1974
(i) KARL - The Karlsruhe Architectural and Register Transfer Language - A draft specification; Skriptum, Fakultät für Informatik, Universität Karlsruhe, 1974
(B) (Hrsg., zus. mit R. Zaks) Microarchitecture of Computer Systems; North Holland Publ. Co./American Elsevier, Amsterdam/New York 1975
(b) Steps toward a Methodology of Integrated Hardware/Software Engineering; in: Proceedings of the 8th HICSS - Hawaii International Conference on System Sciences, University of Hawaii, Honolulu, 1975
(g) (zus. mit G. Koch) The Universal Bus Considered Harmful; in: [45. ]
(n) The use of the block diagram language ABL; in: (Hrsg.: R. Piloty) Proceedings of the Intl. Workshop on Computer Hardware Description Languages, Darmstadt, 1974, ACM Lecture Notes, German Chapter ACM 1975
(n) The use of KARL for the description of Integrated Circuits; in: (s. [48. ])
(b) Hardware Description Languages to Cope with the Complexity of Large Digital Systems; in: (Ed.: A. Madey) Proc. of the IFIP INFOPOL 1976 Intl. Conference on Data Processing, Warsaw, Poland, North Holland Publ. Co./American Elsevier, Amsterdam/New York 1977
(B) Fundamentals of Structured Hardware Design - A Design Language Approach at Register Level; North Holland, Amsterdam/New York 1977
(B) System Development and Development Systems; EUROMICRO, Paris, 1977
(g) (zus. mit W. Keller, Th. Siebold) A Compiler for the Computer Hardware Description Language KARL; in: (Hrsg.: W. Giloi, H. Schindler) Kurzvorträge für die 8. Jahrestagung der Gesellschaft für Informatik, Berlin 1978
(g) (zus. mit K. Rosebrock, K. Hubschneider, R. Wiedemann) Ein SC/MP Multi-Mikrorechner-System zur Straßenverkehrs-Datenerfassung; Tagungsband zur PDV-Fachtagung über Mikrorechner-Anwendung in der Prozeßdatenverarbeitung, Kernforschungszentrum Karlsruhe 1978 - translation of title -
(b) (zus. mit E. von Puttkamer) Ansätze für integrierten Hardware/ Software-Entwurf; in: (Hrsg.: G. Hommel) Verfahren und Hilfsmittel für Spezifikation und Entwurf von Prozeßautomatisierungssystemen, PDV-Bericht, KFK-PDV 154, Juni 1978, Kernforschungszentrum Karlsruhe - translation of title -
(k) (keynote address) LSI Design - from evolution to revolution ?; in: (Hrsg.: F. Vajda) Preprints of uP 1979 - Int'l Conf. on Microcomputers and Applications, Budapest, Hungary 1979
(g) Verallgemeinerung der Prinzipien mikroprogrammierbarer Rechnerstrukturen; in: (Hrsg.: K. Berg) Fachgespräche über Mikroprogrammierung, Gesellschaft für Informatik, Berlin 1979 - translation of title -
(g) (zus. mit E. von Puttkamer) Loosely Coupled Micros as Distributed Function Architecture: a Design Kit and Development Tool; in: (Eds.: J. Tiberghien, G. Carlstedt), Preprints of the 5th Intl. EUROMICRO-Symposium on Microprogramming and Microprocessing, Göteborg, Sweden, 1979
(g) (zus. mit E. von Puttkamer) KARL Compiler with graphic block diagram Input for LSI Chip Design; in: Preprints of the International Conference on Computer Hardware Description Languages and their Applications, Palo Alto, CA, Oct. 1979
(i) (m. P. Liell, E. Schaaf, B. Weber) The grammar of KARL-2; Un. Kaiserslautern 1979
(b) The use of ABL (A Block Diagram Language); in: (Ed.: Y. Chu) Introducing Hardware Description Languages, Prentice-Hall, Englewood Cliffs, N.J. (das Buch ist nicht erschienen)
(i) Memo on VLSI research and developement funding; Univ. Kaiserslautern, 1979
(i) (zus. mit J. Dieckmann) Local Micro Network to support Software Modularity; report, FB Informatik, Universität Kaiserslautern, 1980
(n) Wiring Algebra for Specification of VLSI Design Problems; SIGDA Newsl., Aug. 1980
(b) (zus. mit G. Mußtopf) The consequences of microelectronics onto education in the computer science field; Proc. IFIP-WG. 3.1, Working Conference on Microcomputers and secondary education, Paris, April 1980
(i) (zus. mit E. von Puttkamer) Ist die Informatik eine Ingenieur-Wissenschaft?; unveröffentliches Manuskript, Kaiserslautern 1980 - translation of title -
(i) Curriculums-Überlegungen über die Rolle der Hardware in der Informatik; interner Bericht, 1980 - translation of title -
(g) (zus. mit J. Diekmann) The ESRA Network Kit for Hardware-aided Support of Software Reliability; ICCC, Intl.Conf. on Computers and Circuits, Port Chester, New York, Okt. 1980
(i) Innovations-Schübe der VLSI-Technologie; Memo, Univ. Kaiserslautern 1980 - translation of title -
(bj) VLSI-Bausteine in geringen Stückzahlen und für Spezialanwendungen; Elektronische Rechenanlagen 3, Bd. 22 (1980) - translation of title -
(g) (zus. mit J. Diekmann, W. Konrad) A Local Micro Network to Support Software Modularity; EUROMICRO-Symposium, London, Sept. 1980
(g) (zus. mit J. Diekmann, W. Konrad) Softwarezuverlässigkeit in Rechnernetz-Baukästen verteilter Programmierung, ACM German Chapter Workshop on Hardware for Software, Konstanz, Okt. 1980 - translation of title -
(bj) Basics of Structured Design Methodologies: Data Path and Finite State Machinesin: (eds.: P. Jespers, C. Sequin) Design Methodologies for Very Large Scale Integrated Circuits, Stijthoff & Noordhoff Int´l. Publishing Co., Germantown, MD, 1980
(bj) Shared Culture: CIF Library, Starting Frames, Scalable Design Rules,(eds.: P. Jespers, C. Sequin) Design Methodologies for Very Large Scale Integrated Circuits, Stijthoff & Noordhoff, Germantown, MD, 1980
(i) (zus. mit H. Bellm, J. Diekmann, M. Flötotto, W. Konrad, A. Sauer, W. Schmitter) Die Realisierung des ESRA-Rechnernetz-Baukasten-Systems: ein Ansatz zu einer Methodologie für zuverlässige Software, Bericht, 1980 - translation of title -
(g) (zus. mit P. Liell, E. Schaaf, B. Weber) Eine PASCAL-Implementierung der Rechnerentwurfssprache KARL, Kurzvorträge für die 10. GI-Jahrestagung, Saarbrücken, Sept. 1980 - translation of title -
(p) "AUF EIN WORT"; DIE WELT, 16. Okt. 1980 - translation of title -
(p) "AUF EIN WORT"; DIE WELT, 11. Dez. 1980 - translation of title -
(b) Tutorial on VLSI Design (hand-out to participants), 7th EUROMICRO Symposium, Paris, 1981
(p) "AUF EIN WORT"; DIE WELT, 7. Jan. 1981 - translation of title -
(i) (m. P. Liell, E. Schaaf, B. Weber) CHARLES - A Register Transfer Language for Hardware Design and Specification, report, Berkeley/Kaiserslautern, 1981
(i) (m. P. Liell, E. Schaaf) The Grammar of KARL 2; Bericht, Kaiserslautern 1981
(i) (zus. mit P. Liell, E. Schaaf, B. Weber) KARL user manual and introduction; report Berkeley/Kaiserslautern, 1981
(B) (Hrsg. zus. mit Melvin Breuer) Computer Hardware Description Languages and their Applications; North Holland Publ.Co, Amsterdam/New York, 1981
(b) Run time diagnostics of faults and communication indigestion in a loosely coupled local mircocomputer network, in (Hrsg.: P. Dal Cin, E. Dilger), Proc. Workshop on Self-Diagnosis and Fault Tolerance (Tübingen 1981) Hanser-Verlag, München 1982
(i,b) Zwischenbericht - Einführung der Neuen Mikroelektronik (Mead-&-Conway-Methode) in der Bundesrepublik; Universität kaiserslautern 1982 - translation of title -
(b) KARL-II eine Sprache zur Spezifikation beim Entwurf kundenspezifischer Digitalbausteine; Angewandte Informatik; 12/1982
(p) "AUF EIN WORT"; DIE WELT, 13. Mai 1982 - translation of title -
(bj) (Leitartikel) "VLSI: Wir stehen erst am Anfang"; ELEKTRONIK, 28. Okt. 1982 - translation of title -
(i) (m. P. Liell) Specification of the KARL-III language ; Kaiserslautern, June 1983
(i) (m. P. Liell) KARL-II Language Reference Manual, report, Kaiserslautern 1983
(i) (mit A. Mavridis) RTCode Instant; CVT report, Kaiserslautern, 1983
(i) Specification of the KARL-III language; CVT report; Kaiserslautern, 1983
(i) KARL-II application notes; CVT- report; Kaiserslautern, 1983
(i) (m. G. Girardi) ABL-Specification -Draft-; CVT-report, Torino, Italy / Kaiserslautern, 1983
(b) Innovationen der Neuen Mikroelektronik durch neue Lehrmethoden in Elektrotechnik und Informatik, (Hrsg. U. Baitinger, H. Lipp:) Festschrift zur 25-Jahrfeier des Inst. f. Technik der Informationsverarbeitung, Univ. Karlsruhe, 1983 - translation of title -
(b) VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1983 - translation of title -
(p) "AUF EIN WORT"; DIE WELT, 24. Okt. 1983 - translation of title -
(p) "Deutschland in der Rolle eines Entwicklungslandes"; WELT am SONNTAG, 1983 - translation of title -
(g) (zus. m. G. Girardi, U. Welters): ABLED - ein CAD-Hilfsmittel für den Entwurf digitaler Systeme; DECUS München Symposium, Stuttgart 1983 (Version v. 102) - translation of title -
(i) (m. K. Lemmert) KARL-III reference manual; CVT report, Kaiserslautern 1984
(i) (zus. mit B. Borrmann) Die Übertragung von superKarl-Konstrukten in die Hardware-Beschreibungssprache KARL; report, Kaiserslautern, Mai 1984 - translation of title -
(i) (m. B. Borrmann) superKARL-III Specification; CVT report, Kaiserslautern, 1984
(b) VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1984 - translation of title -
(i) (zus. mit J. Bloedel, R.Hauck, M. Ryba, H.Salzmann, M.Weber) PISA user manual; report, Kaiserslautern 1985
(i) (zus. mit R.Hauck, A.Hirschbiel, W.Nebel, M.Weber) PISA - A CAD package and special hardware for pixel-oriented layout analysis, ICCAD, Santa Clara, 1984, IEEE, New York 1984
(g) (zus. mit K. Lemmert) Entwurfs-Konzeption und Spezifikation von Digital-Hardware, gelenkt durch eine Entwurfs-Sprache, Proceedings, 11. Internationaler Mikroelektronik-Kongress, München 1984 - translation of title -
(i) (zus. mit A. Wodtko:) Automatic Generation of Functional Test Patterns from RT Language Source; Interner Bericht; Kaiserslautern, März 1985
(i) Kaiserslauterns CAD Activities within the CVT Project; interner Bericht 125/85, Fachbereich Informatik, Universität Kaiserslautern, 1985
(i) (zus. mit G. Girardi) ABLED - a RT Level Schematic Editor and Simulator Unser Interface; CVT report; Turin / Kaiserslautern 1985
(g) (zus. mit A Wodtko) Automatic generation of Functional Test Patterns from RT-language source ; Int'l EUROMICRO Symposium; Brussels, Belgium, 1985, North Holland Publishing Co, Amsterdam 1985
(g) (zus. mit G. Girardi, U. Welters) ABLED: a RT level Schematic Editor and Simulator user Interface; Int`l EUROMICRO Symposium, Brussels, 1985, North Holland Publishing Co, Amsterdam 1985
(i) KARL-III Primer (draft), CVT report, Kaiserslautern, April 1985
(i) (zus. mit R. Hauck) KARL language update, CVT report, Kaiserslautern,1985
(i) (zus. mit K. Lemmert) The Hardware Description Language KARL-III: its Integration into a CAD Tool Box; report, Kaiserslautern 1985
(i) (zus. mit G. Alfs, A. Wodtko) C-Testable Cells for ATPG from RT Descriptions; report; Kaiserslautern 1985
(i) (zus. mit A. Wodtko) Functional Test Generation within the KARL-III System; report, Kaiserslautern 1985
(i) (zus. mit W. Nebel) EDIF-based Notation for Layout/Circuit Relations: toward Technnology-Independance of CAD Tools; report; Kaiserslautern 1985
(g) (zus. mit K. Bastian, W. Nebel) VLSI-Algorithmen: innovative Schaltungstechnik statt Software; Tagung Mikroelektronik in der Automatisierungstechnik der Gesellschaft für Meß- und Regelungstechnik, Baden-Baden 1985; VDI-Berichte 550, Düsseldorf 1985 - translation of title -
(b) VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1985 - translation of title -
(b) VLSI-System-Entwurf für Manager; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 2-tägiger Kurs in Oberpfaffenhofen (Bayern) 1985 - translation of title -
(i) (zus. mit K. Lemmert, A. Wodtko) KARL-III Language Reference, second edition (completely rewritten), Kaiserslautern, March 1986
(i) (zus. mit R. Hauck) Design of Symbolic Layout using RT Level CAD Tools; report, Kaiserslautern 1986
(i) (zus. mit W. Nebel) REX: a new CAD Tool shifts Functional Circuit Verification towards RT level; report, Kaiserslautern, 1986
(g) (zus. mit R. Hauck) Entwurf von Symbolischem Layout mit Werkzeugen der Register-Transfer-Ebene; 2. E.I.S.-Workshop, Bonn 1986 - translation of title -
(i) (zus. mit R. Hauck) Die Ableitung von Verhaltens-Beschreibungen aus Matrix-orientiertem Layout; report, Kaiserslautern, 1986 - translation of title -
(g) dto.: 2. E.I.S.-Workshop, Bonn, 1986 - translation of title -
(i) (zus. mit R. Hauck) A simple Silicon Synthesizer for MOL circuits; report, Kaiserslautern, 1986
(i) (zus. mit R. Hauck) Recursive Cell Declarations in a RT Language; report, Kaiserslautern, 1986
(i) (zus. mit R. Hauck, A. Hirschbiel:) A KARL simulator Physical Model Extension; report, Kaiserslautern, 1986
(B) (Hrsg.) Hardware Description Languages; Band 7 der Reihe Advances in CAD for VLSI, North Holland, Amsterdam/New York, 1986
(b) KARL (textuell) und ABL (graphisch): Eine Anwender/Designer-Schnittstelle in der Mikroelektronik; in (Hrsg.: J. Encarnaçao) CAD-Schnittstellen und Datenformate im Elektronik-Bereich, ZGDV-Reihe, Springer-Verlag, Berlin/Heidelberg/New York 1986 - translation of title -
(b) (zusammen mit U. Welters) RT level CAD tools and simulation, in (Ed.: G. Fichtner, M. Morf) VLSI-Tools and Applications (IFIP summer school, Beatenberg, Switzerland), Kluwer Publishing Co., 1986
(g) (zus. mit K. Lemmert) The KARL Compiler and Simulator, the Core of a CAD Tool Box; Proc. EUROMICRO Symposium, Venice, Italy, 1986, North Holland Publ. Co, Amsterdam 1986 (noch nicht erschienen)
(bj, p) Ausbruch der E.I.S.-Zeit; Titelgeschichte: Computer Magazin 3 (März) 1986 - translation of title -
(b,p) Der Mikroelektronik-Markt und Neue Infrastrukturen; VDI-Nachrichten, 29. August 1986 - translation of title -
(k) CAD-Hilfsmittel hoeherer methodologischer Ebenen: CD - Conceptual Design; Professorenkonferenz "Nachrichtenechnik im Zeichen der Mikroelektronik" im Fernmeldetechnischen Zentralamt, Darmstadt, 1987
(i) Technische Informatik II, Skriptum zur Vorlesung, Fachbereich für Informatik, Universität Kaiserslautern, 1987 - translation of title -
(b) (m. G. Girardi, U. Welters): ABL - an interactive graphic user interface in microelectronics; in: J. Encarnaçao: CAD-Schnittstellen und Datentransferformate im Elektronik- Bereich; Springer-Verlag, 1987
(b) Simulation von VLSI-Schaltungen; CAD-CAM REPORT, Febr. 1987
(gj) (m. U. Welters): Higher Level Simulation and CHDLs, in: Fichtner/ Morf: VLSI CAD Tools and Applications, Kluwer Academic Publishers, 1987
(g) (m. J. Blödel, W. Nebel, M. Ryba): A Technology Description Method for Generalized Layout/Circuit Relations; in: EUROMICRO '87, Short Notes Programme, edited by John Mølgaard, Portmouth, U.K. Sept. 14-17, 1987
(g) (m. J. Blödel, M. Ryba): PAGE · An ELL(1) Based EDIF Parser Generator; Proceedings of the European EDIF Forum, Brussels, Belgium, Sept. 30, 1987
(g) (m. J. Blödel, W. Nebel, M. Ryba): Automatische Extraktion von Register-Transfer-Beschreibungen aus geometrischem Layout integrierter Schaltungen; in: Tagungsband des 3. E.I.S. Workshops, Bonn, 13./14. Oktober 1987 - translation of title -
(g) (m. J. Blödel, W. Nebel, M. Ryba): EDIF Notation for Layout / Circuit Relations; in: Proceedings of the IFIP WG 10.2 Workshop on Tool Integration and Design Environments, edited by F.J. Rammig, Paderborn, 26-27 Nov. 1987
(g) (m. U. Welters): MLED: A Multiple Abstraction Level Graphical Editor; Proceedings of the EUROMICRO '87 Symposium; Portsmouth; UK, Sept. 1987
(g) (m. U. Welters): Mehrebenen-Graphik-Editor als DBMS für Simulations- Umgebungen; ASIM '87 - 4. Symposium Simulationstechnik; ETH Zürich, Switzerland, Sept. 1987
(g) (m. R. Hauck): Functional Extraction from Personality Matrixes of MOL (Matrix-Oriented Logic) Circuits; IFIP CHDL'87, Amsterdam, Holland, 1987
(g) (m. A.Hirschbiel, M. Weber): MOM - Map Oriented Machine, Proceedings of the International Workshop on Hardware Accelerators, Oxford, UK Oct. 1987
(g) (m. A.Hirschbiel, M.Weber): MOM - Map Oriented Machine, Conference on Parallel Processing and Applications, L'Aquila, Italy, Sept. 1987.
(g) (m. A.Hirschbiel, M.Weber): A Flexible Architecture for Image Processing, Proceedings of the EUROMICRO Symposium, Portsmouth, UK, 1987.
(g) (m. W. Nebel): Shifting Functional Design Verification Towards RT Level by Automatic Register Transfer Net Extraction; IFIP CHDL'87, Amsterdam, 1987
(g) (m. W. Nebel): Functional Design Verification by Register Transfer Net Extraction from Integrated Circuit Layout Data; IEEE COMPEURO, Hamburg, 1987
(i) (m. A.Bonomo, G.Girardi, L.Lavagno, R. Hauck): Syntax Diagrams of the CVS_BK Language (CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy / Informatics Dept., Univ. Kaiserslautern, F.R.G., Febr. 1987
(i) (m. A.Bonomo, G.Girardi, L.Lavagno, R.Hauck): Semantic Specification of CVS_BK Language (CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy / Informatics Dept., Universität Kaiserslautern, F.R.G., Febr. 1987
(i) Entwurf eines Universalprozessors mit Hocharchitektur, Universität Kaiserslautern, 1986 - translation of title -
(i) Proposal of a High Level Hardware Description Language; ESPRIT / CVS report, Informatics Dept., Universität Kaiserslautern, Sept. 1986
(i) (m. R. Hauck): Simulator Specification for CVS_BK; ESPRIT/ CVS report, Informatics Dept., Universität Kaiserslautern, Febr. 1987
(i) (m. R. Hauck): A Behavioural / Non-procedural Mixed-Level Simulator for Digital VLSI Systems; ESPRIT report, CS Dept., Univ. Kaiserslautern, Febr. 1987
(i) (m. R. Hauck, K. Lemmert, A. Wodtko): KARL-4 and SCIL-3 Grammar (Draft); ESPRIT / CVS report, Dept. of Computer Science, Kaiserslautern Univ., July 1987
(i) (m. R. Heinen): Benutzungsanleitung für KARL-3 auf ATARI-ST; Bericht, Fachbereich Informatik, Universität Kaiserslautern, 1987 - translation of title -
(i) (m. G.Alfs): Design and Implementation of a Heuristic Search Algorithm for the KARATE System; Interner Bericht Nr. 183 / 88, Fachbereich Informatik, Universität Kaiserslautern, 1987
(i) (m. J.Blödel, W.Nebel, M.Ryba): EDIF Notation for Layout / Circuit Relations; Interner Bericht Nr. 179 / 88, Fachbereich Informatik, Univ. Kaiserslautern, 1987
(i) (m. J.Blödel, W.Nebel, M.Ryba): Automatische Extraktion von Register-Transfer-Beschreibungen aus dem Layout integrierter Schaltungen Interner Bericht Nr. 180 / 88, Fachbereich Informatik, Universität Kaiserslautern, 1987 - translation of title -
(i) (m. A.Hirschbiel, M.Weber): MOM - Map Oriented Machine - An Innovative Computing Architecture; Interner Bericht Nr. 181 / 88, Fachbereich Informatik, Universität Kaiserslautern, 1987
(b) VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1987 - translation of title -
(b) VLSI-System-Entwurf für Manager; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 2-tägiger Kurs in Oberpfaffenhofen (Bayern) 1987 - translation of title -
(g) (m. J.Blödel, W.Nebel, M.Ryba) EDIF Notation for Layout/Circuit Relations in: F.J.Rammig (ed.) : Tool Integration and Design Environments, North Holland, Amsterdam / New York 1988
(g) (m. J.Blödel, W.Nebel, M.Ryba): A Technology Description Method for Generalized Layout/Circuit Relations in: Microprocessing and Microprogramming 23, North Holland, Amsterdam / New York, 1988, pp. 15 - 20
(g) (m. A.Hirschbiel, M.Weber): MOM - Map oriented Machine; in: E.Chiricozzi & A.D'Amico : Parallel Processing and Applications, North-Holland, Amsterdam / New York, 1988
(g) (m. A.Hirschbiel, M.Weber): MOM - Map oriented Machine; in: Ambler, Agrawal, Moore: Hardware Accelerators, Adam Hilger, 1988
(g) (m. A.Hirschbiel, M.Weber): Patil Array - A Petri Net Hardware Implementation in : Tagungsband zur COMPEURO '88, IEEE Press, Washington, D.C., 1988
(g) (m. K.W.Jörg, U.Welters): MLED - Ein Mehrebenen-Graphik-Editor für den VLSI Entwurf; in: Valk (ed.): Proceedings 18. GI-Jahrestagung, Springer-Verlag, Berlin / Heidelberg / New York, 1988 - translation of title -
(g) (m. M.Ryba): Partitionierungsschemata für Rechnerstrukturen; in : Valk (ed.) : Proceedings 18. GI-Jahrestagung, Springer-Verlag, Berlin / Heidelberg / New York, 1988 - translation of title -
(g) (m. G.Alfs, M.Riedmüller): SCIL-III - a language for simulator and tester activation; Proceedings of the 2nd ABAKUS Workshop, Innsbruck,Austria, 1988
(g) (m. G.Alfs, A.Wodtko): The KARATE system - Integrating functional test development into the KARL design environment; Proceedings of the 2nd ABAKUS Workshop, Innsbruck, Austria, 1988
(g) (m. G.Alfs, A.Wodtko): The KARL/KARATE system : Automatic Test Pattern Generation Based on RT Level Descriptions; Proceedings of the International Test Conference, Washington DC, USA, 1988
(g) (m. G.Alfs, M.Riedmüller, A.Wodtko): Integration of Simulation, Test Development and Test in a High Level Design Environment; Proceedings of the IFIP TC10 Working Conference, Pisa, Italy, 1988
(g) (m. G.Alfs, A.Wodtko): The KARL/KARATE system : Integrating Functional Test Development into a CAD Environment for VLSI; Proceedings of the International Conference on Computer Design, Port Chester, NY, USA, 1988
(g) (m. G.Alfs, A.Wodtko): Integration der Testentwicklung in den Entwurf von Vollkundenschaltungen; ITG Fachbericht 103, ITG Fachtagung Mikroelektronik für die Informationstechnik, Berlin, 1988 -translation of title -
(g) (m. J.Blödel, M.Ryba): EDIF Notation for the Description of Universal Rules for Parameter and Device Extraction from Mask Layout; 4th E.D.I.F. User Group Workshop, Digest of Technical Papers, Colorado Springs, CO, U.S.A., 1988
(g) (m. J.Blödel, M.Ryba): PAGE - An ELL(1) based EDIF Parser Generator; Proceedings of the 2nd European EDIF Forum, Amsterdam, Holland, 1988
(g) (m. J.Blödel, M.Dörr, M.Ryba): AMBROSE : Advanced Modular Browsing System for EDIF Graphical Data; Proceedings of the 2nd European EDIF Forum, Amsterdam, Holland, 1988
(g) (m. J.Blödel): The Work and the Activities of the European EDIF Working group Technology - A Survey; Proceedings of the 2nd European EDIF Forum, Amsterdam, Holland, 1988
(g) (m. R.Hauck, K.Lemmert): Some new features in KARL-4 and superKARL - a survey; Proceedings of the 2nd ABAKUS Workshop, Innsbruck, Austria, 1988
(g) (m. K.W.Jörg, U.Welters): MLED - A multiple view graphics editor for VLSI design; Proc. 2nd ABAKUS Workshop, Innsbruck, Austria, 1988
(g) (m. K.Lemmert ): A systolic design system using KARL; Proceedings of the 2nd ABAKUS Workshop, Innsbruck, Austria, 1988
(g) (m. R.Hauck): KARL-4 - A hardware description language for the design and synthesis of digital hardware; Proc. 2nd ABAKUS Workshop, Innsbruck, Austria, 1988
(b) VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1988 - translation of title -
(b) VLSI-System-Entwurf für Manager; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 2-tägiger Kurs in Oberpfaffenhofen (Bayern) 1988 - translation of title -
(g) (m. K. Lemmert): CHDL-Based CAD System for the Synthesis of Systolic Architectures; in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London 1989.
(g) (m. A.G. Hirschbiel, M.Weber): Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London 1989.
(b) Xputer: Rechner nach neuartigen Prinzipien; GI Informatik Spektrum, Dezember 1989, Springer-Verlag, Berlin / Heidelberg / New York, 1989. - translation of title -
(b) Der Rechner aus dem Elfenbeinturm; Markt & Technik, Nr. 44/89, Okt. 1989. - translation of title -
(g) (m. G. Alfs, A. Ast, A. Wodtko): Explizite Fehlermodellierung mit dem KARATE- System; Proceedings 4. E.I.S.-Workshop, GMD- Studien Nr.155, St Augustin, 1989 - translation of title -
(g) (m. G.Alfs, A. Wodtko): Explicit Fault Modelling and Hierarchical Test Pattern Generation in the KARATE-System; Proc. EUROMICRO 1989, North Holland/American Elsevier,1989.
(g) (m. J. Blödel): Extending EDIF for Technology Adaptable Mask Artwork Synthesis, 5th EDIF User Group Workshop Digest of Techn.Papers, San Jose, CA, USA, Sept 1989
(b) (m. J. Blödel): Extending EDIF for Technology Adaptable Mask Artwork Synthesis, 3rd European EDIF Forum, Königswinter, October 1989
(g) (m. J. Blödel): Extending EDIF for Technology Adaptable Mask Artwork Synthesis; Poster-Session 3rd European EDIF Forum, Königswinter, Okt. 1989.
(g) (m. K. Lemmert, M. Riedmüller): Synthesis of Systolic Architectures Using the SYS3-System; in: EUROMICRO Symposium '89, Köln, Elsevier Science Publishers, 1989
(g) (m. K. Lemmert): SYS3 - A CHDL-Based Systolic Synthesis System, in: Proc.CHDL'89, Washington, D.C., U.S.A., Elsevier, 1989
(g) (m. K. Lemmert): SYS3 - Ein systolisches Synthesesystem; Proceedings 4.E.I.S.-Workshop, GMD-Studien Nr.155, Sankt Augustin, 1989 - translation of title -
(g) (m. A.G. Hirschbiel, M.Weber): MOM - a partly custom-design architecture compared to standard hardware, Proc. IEEE Compeuro, Hamburg 1989, IEEE Press, 1989.
(g) (m. A.G. Hirschbiel, M.Weber): A Pseudo Parallel Architecture for Systolic Algorithms. Proc. of the International Conference on VLSI and CAD, Seoul, Korea, 1989
(g) (m. A.G. Hirschbiel, M.Weber): A Pseudo Parallel Architecture for Systolic Algorithms. Proc. of the IFIP Workshop on Parallel Architectures on Silicon, Grenoble, France, Dec.89.
(g) (m. M. Schubert, J. Blödel et al.): Extending EDIF for Technology Data, 5th EDIF Users Group Workshop Digest of Technical Papers, San Jose, CA., USA, September 1989
(g) (m. M. Schubert, J. Blödel et al.): Extending EDIF for Technology Data, 3rd European EDIF Forum, Königswinter, October 1989.
(b) VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1989
(i) (m. R. Hauck): CVS_BK Language Reference Manual; CVS-Bericht; CSELT, Torino (Italy) / Universität Kaiserslautern, 1989
(g) (m. A. Ast, A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): Using Xputers as Inexpensive Universal Accelerators in Digital Signal Processing; Bilkent'90 International Conference on New Trends in Communication, Control and Signal Processing; Ankara, Turkey, Juli 1990.
(g) (m. J. Blödel): A Technology Adaptable Device Generator as a Frontend for Layout Synthesis Tools; EDAC '90, Glasgow, UK, März 1990
(g) (m. J. Blödel): A Data Model for VLSI Technology Data, 6th EDIF User Group Workshop - EDIF Worl 1990, New Orleans, LA, USA, September 1990
(g) (m. J. Blödel): A Data Model for VLSI Technology Data; 4th European EDIF Forum, Daresbury, UK, Oktober 1990
(g) (m. A.G. Hirschbiel, M.Weber): Xputers - An Open Family of Non von Neumann Architectures; Proc. of 11th ITG/GI-Conference: Architektur von Rechensystemen, München, März 1990, VDE-Verlag, Berlin, 1990.
(g) (m. A.G. Hirschbiel, M.Weber): The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; International Workshop on Algorithms and Parallel VLSI Architectures, Pont-à-Mousson, France, June 1990
(g) (m. A.G. Hirschbiel, M.Weber): Using Xputers as Universal Accelerators for Neuro Network Simulation and its Applications; International Neural Network Conference, INNC 90, Paris, France, Juli 1990.
(g) (m. A.G. Hirschbiel, M.Weber): The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; 1990 International Conference on Parallel Processing, St. Charles, Illinois, USA, August 1990.
(g) (m. A.G. Hirschbiel, M.Weber): A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; CONPAR '90 - VAPP IV, Zürich, Schweiz, September 1990.
(g) (m. A.G. Hirschbiel, K. Schmidt, M.Weber): A Novel ASIC Design Approach based on a New Machine Paradigm; European Solid-State Circuits Conference '90, Grenoble, France, September 1990.
(g) (m. A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Preprocessing; 12. DAGM-Symposium Mustererkennung, Oberkochen-Aalen, Sept. 1990.
(g) (m. A.G. Hirschbiel, K.Lemmert, M. Riedmüller, K. Schmidt, M.Weber:) Xputer Use in Image Processing and Digital Signal Processing; SPIE Visual Communication and Image Processing'90, Lausanne, Schweiz, Oktober 1990.
(g) (m. A.G. Hirschbiel, M.Weber): Xputers: Very High Throughput by Innovative Computing Principles; 5th Jerusalem Conference on Information Technology (JCIT), Jerusalem, Israel, October 1990, IEEE Computer Society Press, 1990.
(g) (m. A. G. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber): A Flexible Hardware Accelerator and its Applications in EDA; 16th CAVE Workshop in Gent, Belgium, Dezember 1990
(b) (m. A.G. Hirschbiel, M.Weber): Rekonfigurierbare ALU erlaubt Parallelisierung auf unterster Ebene; VMEbus, Februar 1990. -translation of title -
(i) (m. A. Ast, P. Bittner, J. Blödel, M. Weber, U. Zahm): Anforderungen an die WZ-Schnittstelle aus Tool-Sicht: Bericht DASSY-Projekt, Universität Kaiserslautern, Fachbereich für Informatik, Februar 1990 - translation of title -
(i) (m. A. Ast, J. Blödel): Technology Data for Circuit Extraction and Layout Synthesis: Report DASSY-Project, Universität Kaiserslautern, März 1990
(i) (m. A. Ast, J. Blödel): Anforderungen an eine Werkzeugschnittstelle für Digitalsimulatoren und Testerzeuger auf der RT-Ebene, Bericht DASSY-Projekt, Universität Kaiserslautern, Fachbereich für Informatik, März 1990 -translation of title -
(i) (m. A. Ast, J. Blödel): Configuration Data for fault-model independent Automatic Test Generators; Bericht zum DASSY-Project, Universität Kaiserslautern, Fachbereich für Informatik, März 1990
(i) (m. A. Ast, J. Blödel et. al.): Anforderungen an die Werkzeugschnittstelle aus Sicht der Tools; Bericht zum DASSY-Projekt, Gesellschaft für Mathematik und Datenverarbeitung, St. Augustin, März 1990 - translation of title -
(i) (m. A. Ast, J. Blödel, U. Jasnoch, J. Reedmer, M. Ungerer): Konzept der prozeduralen Werkzeugschnittstelle im DASSY-Prototypen; Bericht DASSY-Projekt, Universität Kaiserslautern / Technische Hoch-schule Darmstadt, Okt. 1990 -translation of title -
(i) (m. J. Blödel et. al.): General Unit Definition for EDIF; EDIF Device Modeling & Verification TSC (Technical Subcommittee), Proposal DM&V No. 1, May 1990
(i) (m. J. Blödel): Topological Device Descripiton for EDIF; Report EDIF Device Modeling & Verification; IEEE EDIF Standardization Committee, TSC (Technical Subcommittee) on Technology, August 1990
(i) (m. A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Universität Kaiserslautern, Fachbereich für Informatik, 1990
(bj) (m. A.G. Hirschbiel, M.Weber): Rekonfigurierbare ALU erlaubt Parallelisierung auf unterster Ebene; VMEbus, Februar 1990. -translation of title
(g) Xputer: ein neues Maschinen-Paradigma für Höchstleistungsrechner; Lessacher Informatik-Kolloquien, Lessach, Austria, 18.-21. September 1990, Springer-Verlag, Berlin / Heidelberg / New York, 1991 - translation of title -
(g) (m. A.G. Hirschbiel, M.Weber): A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90- International Conference memorating the 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990 Invited reprint in Future Generation Computer Systems 7 91/92, p. 181-198, North Holland
(g) (m. A. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): A Novel high-performance Machine Paradigm Using Auto-sequencing Data Memory; 1991 Hawaii International Conference on Systems Sciences, Koloa, Kauai, Hawaii, 1991
(g) (m. A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): A Novel ASIC Design Method based on a Machine Paradigm; IEEE-JSSC - Journal of Solid State Circuits , Vol. 26, No. 7, pp. 975-989, July 1991
(gj) (m. K. Schmidt, H. Reinig, M. Weber): A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic; in Will Moore, Wayne Luk (ed.): Field Programmable Logic and Applications, Abingdon EE&CS Books, Abingdon, 1991
(g) (m. J. Blödel, M. Brandstetter, P. Conradi, W. Drangmeister, P. Jores, M. Ryba, D. Schröder): EDIF Extensions Proposed by the EDIF Device Modelling & Verification TSC; 5th European EDIF Forum; La Grande Motte, France, Oct 10-11, 1991
(g) (m. J. Blödel, P. Conradi): Schnitstellen zwischen CAD und TCAD, 5. E.I.S.-Workshop, Dresden, 8.-9. April 1991 - translation of title -
(g) (m. A. G. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber): A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24 Hawaii Int'l Conference on System Sciences, Koloa Hawaii, January 1991
(g) (m. H. Reinig, M. Riedmüller, K. Schmidt): A Novel Computational Paradigm: Much More Efficient Than Von Neumann Principles; 13th IMACS World Congress, Dublin Ireland, July 1991
(g) (m. K. Schmidt, H. Reinig, M. Weber): A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic; International Workshop on Field Programmable Logic and Applications, Oxford 1991
(i) (m. J. Blödel): Parameterized Topological Device Descriptions, Proposal for EDIF Version 2 0 5, Version 1.0, Report DASSY Projekt, University of Kaiserslautern, January 1991
(i) (m. J. Blödel, M. Brandstetter, W. Drangmeister, D. Schröder): Device Descriptions, EDIF Version 205, Proposal No. DM&V-3 Version 1.0; Interner Bericht Nr. 211/91, Fachbereich Informatik, Universität Kaiserslautern, 31. Mai 1991
(i) (m. J. Blödel, D. Schröder, W. Wilkes): DASSY - Übersicht über die Informationsmodelle; Bericht zum Meilensteintreffen M3; DASSY Projekt; 23. Juli 1991 - translation of title -
(i) (m. J. Blödel): Report on Extraction: Second Periodic Progress Report, PATMOS Projekt, Universität Kaiserslautern, Dezember 1991
(i) (m. M. Riedmüller, K. Schmitt, M. Weber): A Novel Asic Design Approach Basd on a New Machine Paradigm; Interner Bericht 212/91, Universität Kaiserslautern, Fachbereich Informatik, Juli 1991
(i) (m. S. Perdomo, A. Nuñez, et al.): Report on Interconnect Modelling: Second Periodic Progress Report, PATMOS Projekt, Universität Kaiserslautern, Dezember 1991
(bj) (m. A. Ast, et al.): High Performance VLSI Signal Processing; in (Hrsg: M. Bayoumi): VLSI Image and Signal Processing; Kluwer Akademic Publishers, Boston, 1992.
(g) (m. A. Ast, H. Reinig, K. Schmidt, M. Weber): A Novel High-performance Machine Paradigm and ASIC Design Methodology; International Design Automation Workshop (Russian Workshop), 29. - 30. 06. 92, Moskau, 1992
(bj) (m. A. Hierschbiel,K. Schmidt,M. Weber): A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW, Future Generation Computer Systems 7 91/92, p. 181-198, North Holland Invited reprint of InfoJapan'90- International Conference memorating the 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990
(g) (m. A. Ast, et al.): Ein neuartiger Ko-Prozessor zur Akzeleration von Algorithmen mit regelmäßigen Datenabhängigkeiten, GI/ITG Workshop Hochintegrierte Schaltungen für Parallelarchitekturen, 2. - 3.7.92, Irsee, Germany, 1992 - translation of title -
(g) (m. H. Reinig): Der GAG-Adreßgenerator und seine Anwendung als Akzelerator, GI/ITG Workshop Hochintegrierte Schaltungen für Parallelarchitekturen, 2. - 3.7.92, Irsee, Germany, 1992 - translation of title -
(g) (m. A. Ast, et al.): Novel High Performance Machine Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and a Challenge to, Field-programmable Logic ; 2nd International Workshop on Field-Programmable Logic and Applications, 31. 08. - 02. 09. 92, Vienna University of Technology, Vienna Austria, 1992
(g) (m. E. Melcher, M. Dana, et al.): CMOS Interconnect Modelling for Timing Analysis, EUROMICRO Symp., short notes, 14.-17.09.92, Paris, France, 1992
(g) (m. E. Melcher, M. Dana, et al.): Interconnect Characterization of CMOS Circuits for Timing Analysis; Proceedings of the European Workshop on Power and Timing Modelling, 18.09.92, Paris, France, 1992
(g) (m. H. Reinig, M. Weber): Design of an Address Generator, 3rd Eurochip Workshop on VLSI Design Training, 30.9 - 2.10.92, Grenoble, France, 1992
(B) (Edior w. D. Auvergne.): Power and Timing Modelling for Performance of Integrated Circuits; Proceedings of the Third International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS´93), La Grande Motte, France, ISBN 3-929814-04-8, IT Press Verlag, Okt. 1993
(B) H. Grünbacher, R. Hartenstein (Hrsg.): Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping; Lecture Notes in Computer Science, ISBN 3-540-57091-8, Springer-Verlag Berlin/Heidelberg, 1993.
(B) R. Hartenstein: Wozu noch Mikro-Chips? Einführung in Methoden der Technischen Informatik; ISBN 3-929814-00-5, IT Press Verlag, 1993 - translation of title -
(g) KARL and ABL, in J. P. Mermet (Hrsg.): Fundamentals and Standards in Hardware Description Languages; Kluwer Academic Publishers, Dordrecht, pp. 447-466, 1993.
(g) (m. E. Melcher, M. Dana, et al.): CMOS Interconnect Modelling for Timing Analysis; in Microprocessing and Microprogramming, North-Holland, Jan. 1993
(g) Hardware/Software Co-Design; 3rd International Workshop on Field Programmable Logic and Applications, Oxford, UK, Sept. 1993
(g) (m. A. Ast, J. Becker, et al.): MoPL-3: A New High Level Xputer Programming Language; 3rd International Workshop on Field Programmable Logic and Applications, Oxford, UK, Sept. 1993
(g) Xputer: ASIC or Standard Circuit?; (Invited Paper), GME Fachtagung Mikroelektronik, Dresden, VDE-Verlag, Berlin, März 1993
(i) The History of KARL and ABL; (Interner Bericht Nr. 232/93), Fachbereich Informatik, Universität Kaiserslautern, April 1993
(B) (Editor with M. Servít): Field-Programmable Logic: Architectures, Synthesis, and Applications; Lecture Notes in Computer Science, ISBN 3-540-58419-6, Springer-Verlag Berlin/Heidelberg, 1994.
(bj) (m. A. Ast, H. Reinig, K. Schmidt, M. Weber): A General Purpose Xputer Architecture derived from DSP and Image Processing; in M.A. Bayoumi (ed.): VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, p. 365-394, 1994.
(g) (m. H. Reinig, et al.): A Reconfigurable Data-Driven ALU for Xputers; IEEE Workshop on FPGAs for Custom Computing Machines, FCCM'94, Napa, CA., April 1994.
(g) (m. H. Reinig, et al.): An FPGA Architecture for Word-Oriented Datapaths; Canadian Workshop on Field-Programmable Devices, FPD'94, Kingston, Ontario, June 13-16, 1994
(g) (m. H. Reinig, et al.): A Dynamically Reconfigurable Wavefront Array Architecture for Evaluation of Expressions; Proceedings of the Int. Conference on Application-Specific Array Processors, ASAP'94, San Francisco, IEEE Computer Society Press, Los Alamitos, CA, Aug. 1994
(g) (m. H. Reinig, et al.): A Reconfigurable Arithmetic Datapath Architecture: GI/ITG-Workshop, Schloß Dagstuhl, Bericht 303, pp. 53-59, Juli 1994
(g) (m. H. Reinig, et al.): A New FPGA Architecture for Word-oriented Datapaths; 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994
(g) (m. A. Ast, J. Becker, et al.): Data-procedural Languages for FPL-based Machines; 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994.
(g) (m. Karin Schmidt): Parallelizing Compilation for a Novel Data-Parallel Architecture; J. P. Gray, F. Naghdy (Eds.), PCAT-94, Parallel Computing: Technology and Practice, Wollongong, Australia, pp. 126-137, Nov. 1994
(g) (m. K. Schmidt): A Restructuring Compilation Method for the Xputer Paradigm: IWPP 94, Proceedings of the Int. Workshop on Parallel Processing, Bangalore, India, Dec. 1994
(i) Hardware/Software Codesign; Internal Report No. 246/94, University of Kaiserslautern, 1994.
(bj) Algebraischer Entwurf regelmaessiger Schaltungen; in: R. Hartenstein: Standort Deutschland: Wozu noch Mikrochips? Einfuehrrung in methoden der Technischen Informatik; ITpress Verlag, 1994 -- pdf -- fm

(g) (m. K. Schmidt): Combining Structural and Procedural Programming by Parallelizing Compilation; Proceedings of the Symposium on Applied Computing, Nashville, TN, Feb. 1995
(bj) (m. J. Becker, et al.): High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1996
(bj) (m. J. Becker, et al.): A Novel Machine Paradigm to Accelerate Scientific Computing; Computer Science and Informatics Journal, Special Issue of Scientific Computing, Computer Society of India, 1996
(gj) (m. J. Becker, et al.): A Novel Two-Level Hardware/Software Co-Design Framework; Journal of the Brazilian Computer Society, Special Issue on Electronic Design Automation, Dec. 1995
(gj) Hardware/Software Co-Design; GI Informatik-Spektrum, 1995 - translation of title -
(gj) Custom Computing Machinmes; GI Informatik-Spektrum, 1995
(g) (m. J. Becker, et al.): CoDe-X: A Novel Two-Level Hardware/Software Co-Design Framework; 9th International Conference on VLSI Design, Bangalore, India, Jan. 1996
(g) (m. J. Becker, et al.): A Reconfigurable Parallel Architecture to Accelerate Scientific Computation; International Conference on High Performance Computing, New Delhi, India, Dec. 1995
(g) (m. J. Becker, et al.): A Profiling-driven Hardware/Software Partitioning of High-Level Language Specifications; Workshop on Logic and Architecture Synthesis, Grenoble, France, Dec. 1995
(b) Custom Computing Machines - an overview (invited talk); Workshop on Design Methodologies for Microelectronics, DMM'95, Smolenice Castle, Czech Republic, Sept. 1995
(g) (m. J. Becker, et al.): A Two-Level Hardware/Software Co-Design Framework for Automatic Accelerator Generation; Workshop on Design Methodologies for Microelectronics, DMM'95, Smolenice Castle, Czech Republic, pp. 145-152, Sept. 1995
(g) (m. H. Reinig): Novel Sequencer Hardware for High-Speed Signal Processing; Workshop on Design Methodologies for Microelectronics, DMM'95, Smolenice Castle, Czech Republic, Sept. 1995
(g) (m. H. Reinig, et al.): A Scalable, Parallel, and Reconfigurable Datapath Architecture; Sixth International Symposium on IC Technology, Systems & Applications, ISIC'95, Singapore, Sept. 1995
(g) (m. R. Kress): A Datapath Synthesis System for the Reconfigurable Datapath Architecture; Asia and South Pacific Design Automation Conference, ASP-DAC'95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug./Sept. 1995
(g) (m. J. Becker, et al.): A Parallelizing Compilation Method for the Map-oriented Machine; International Conference on Application-Specific Array Processors, ASAP'95, Strasbourg, France, IEEE Computer Society Press, Los Alamitos, CA, July 1995
(g) (m. J. Becker, et al.): High-Performance Computing Using a Reconfigurable Accelerator; High Performance Computing Symposium, HPCS'95, Montreal, Canada, July 1995
(g) (m. H. Reinig, et al.): A Reconfigurable Accelerator for 32-bit Arithmetic; Workshop on Reconfigurable Architectures, Santa Barbara, CA, April 1995
(b) (m. J. Becker, et al.): A Reconfigurable Machine for Applications in Image and Video Compression; European Symposium on Advanced Networks and Services: Conference on Compression Technologies and Standards for Image and Video Compression, Amsterdam, The Netherlands, March 1995
(i) (m. A. Ast, J. Becker, et al.): Data-procedural Languages for FPL-based Machines; Universität Kaiserslautern, Fachbereich Informatik, Interner Bericht, Nr. 264/95, 1995
(g) (m. J. Becker, et al.) "A Profiling-Driven Hardware/Software Partitioning of High Level Language Specification; IFIP International Workshop on Logic and Architecture Synthesis, Grenoble, France, 18. - 19. Dezember 1995
(p) Unsere Gesellschaft hat Null Bock auf High Tech; DIE WELT, 19. Feb. 1996 - translation of title -
(g) (m. J. Becker, et al.) Two-Level Hardware/Software Partitioning Using CoDe-X; IEEE Int'l Workshop on Computer Based System Engineering (CBSE'96), Friedrichshafen, Germany, March 1996
(g) (m. J. Becker, et al.) Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine; ACM/IEEE International Workshop on Hardware/ Software Co-Design Codes/CASHE/DODES'96, Pittsburgh, PA, USA, March 18 - 20, 1996
(g) (with J. Becker, M. Herz, R. Kress, U. Nageldinger:) A Partitioning Programming Environment for a Novel Parallel Architecture; IPPS'96 IEEE International Parallel Processing Symposium, Honolulu, Hawaii, U. S. A., 15 - 19 April 1996 <PDF>
(b) (m. J. Becker, M. Herz, et al.) A Parallelizing Programming Environment for Embeded Xputer-based Accelerators; HPCS; Proc. High Performance Computing Symposium, HPCS'96, Ottawa, Canada, June 1996 <PDF>
(B) Null Bock auf High Tech; Arbeitsplatz-Export: nur wegen zu hoher Löhne?; IT Press, 1996 - ISB N 3-929814-06-4 - translation of title -
(g) (m. R. Kress) An Architecture for Highly Parallel Computer Arithmetic; 2nd International Conference on Highly Parallel Computing Systems (MPCS'96), Ischia, Italy, May 6 - 9, 1996
(g) (m. J. Becker, et al.) Application-specific Microprocessor Design Methodologies: General Model vs. Tinkertoy Approach; GI / ITG Workshop on Custom Computing, Schloß Dagstuhl, Wadern, Germany, 19 - 21 June 1996
(b) (eingeladener Beitrag): High-Performance Computing": über Szenen und Krisen; GI / ITG Workshop on Custom Computing, Schloß Dagstuhl, Wadern, Germany, 19 - 21 June 1996 - translation of title -
(g) (m. J. Becker, M. Herz, et al.); A Synthesis System for Bus-based Wavefront Array Architectures; ASAP'96 International Conference on Application-Specific Systems, Architectures and Processors, Chicago, Ill., USA, 19 - 21 August 1996 <PDF>
(g) (m. J. Becker, et al.): Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized Point of View; 6th International Workshop on Field Programmable Logic and Applications; Darmstadt, Germany, September 23 - 25, 1996
(B) (m. M. Glesner): Field-Programmable Logic; Lecture Notes in Computer Science, Springer-Verlag Berlin/Heidelberg/New York, 1996.
(p) Der neue Treibstoff für Wohlstand und Arbeit ist Wissen; WELT am SONNTAG, 5. 5. 1996 - translation of title -
(p) Schlagkräftige Innovations-Truppen entscheiden den Wettstreit der Nationen; WELT am SONNTAG, 12. 5. 1996 - translation of title -
(p) Die Wettbewerbsfähigkeit muß oberstes Ziel unseres Bildungswesens sein; WELT am SONNTAG, 19. 5. 1996 - translation of title -
(b) (m. J. Becker, M. Herz, et al.): Co-Design and High Performance Computing: Scenes and Crisis; Proc. Reconfigurable Technology for Rapid Product Development & Computing as Part of SPIE's Int'l Symposium VOICE, VIDEO and DATA COMMUNICATIONS, PHOTONICS EAST, Boston, USA, Nov. 1996
(bj) (m. J. Becker, et al.): A Novel Machine Paradigm to Accelerate Scientific Computing; Computer Science and Informatics Journal: Special issue on Scientific Computing, Computer Society of India, 1996
(g) (m. J. Becker, et al.): An Embedded Accelerator for Real Time Image Processing; 8th EUROMICRO Workshop on Real Time Systems, L'Aquila, Italy, June 1996
(g) (m. J. Becker, M. Herz, U. Nageldinger): A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. IEEE 1996 Int. Conference on Innovative Systems in Silicon (ISIS); Austin, Texas, USA, October 9-11, 1996 <PDF>
(g) (m. J. Becker, M. Herz, et al.): Co-Design and High Performance Computing: Scenes and Crisis; Proceedings of Reconfigurable Technologie for Rapid Product Development & Computing, Part of SPIE's International Symposium '96, Boston, USA, Nov. 1996 <PDF>
(g) (m. J. Becker): Hardware/Software Co-Design for data-driven Xputer-based Accelerators; to be published in Proc. 10th Int. Conf. on VLSI Design (Theme: VLSI in Multimedia Applications), January 4-7, 1997, Hyderabad, India
(g) (m. J. Becker): A Two-level Co-Design Framework for data-driven Xputer-based Accelerators; Proc. 30th Hawaii Int. Conf. on System Science (HICSS-30), January 7-10, Wailea, Maui, Hawaii, USA, 1997
(g) (m. J. Becker): Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators; Proc. of 5th Int'l. Workshop on Hardware/Software Co-Design CODES/CASHE'97, Braunschweig, Germany, March 24-26,1997
(g) (m. J.Becker, K. Schmidt): Performance Evaluation in Xputer-based Accelerators; Proc. of 4th Reconfigurable Architectures Workshop RAW-97, in conjunction with 11th Int'l. Parallel Processing Symposium, IPPS'97, Geneva, Switzerland, April 1-5,1997
(b) How to Survive a Possible New Design Crisis; Opening Keynote, to appear in Proceedings of the IFIP WG10.1 & 10.7 Workshop, University of Sterling, UK, July 2-4, 1997
(g) (m. J. Becker, M. Herz, U. Nageldinger):A Novel Sequencer Hardware for Application Specific Computing; Proceedings of 11th International Conference on Application-specific systems, Architectures and Processors, ASAP`97, Zurich, Switzerland, July 14-16, 1997 <PDF>
(g) (m. J. Becker, M. Herz, U. Nageldinger): An Embedded Accelerator for Real World Computing; Proceedings of IFIP International Conference on Very Large Scale Integration, VLSI`97, Gramado, Brazil, August 26-29, 1997 <PDF>
(g) (m. R. Kress, U. Nageldinger): An Operating System for Custom Computing Machines based on the Xputer Paradigm; Proceedings of 7th International Workshop on Field Programmable Logic, FPL`97, London, UK, September 1-3, 1997
(g) (m. J. Becker, M. Herz, U. Nageldinger): Data Scheduling in Hardware/Software Co-Design for Field-programmable Accelerators; Proceedings of 7th International Workshop on Field Programmable Logic, FPL`97, London, UK, September 1-3, 1997 <PDF>
(g) (m. J. Becker, M. Herz, U. Nageldinger): An Innovative Platform for Embedded System Design; Proceedings of the Workshop Zielarchitekturen Eingebetteter Systeme, ZES`97, in conjunction with the Fachtagung Architekturen von Rechensystemen ARCS'97, Rostock, Germany, September 11, 1997 <PDF>
(g) (with. J. Becker, M. Herz, U. Nageldinger): A Novel Universal Sequencer Hardware; Proceedings of Fachtagung Architekturen von Rechensystemen ARCS'97, Rostock, Germany, September 8-11, 1997 <PDF>
(b) The Microprocessor is no more General Purpose: why Future Reconfigurable Platforms will win; invited paper, Proceedings of the International Conference on Innovative Systems in Silicon, ISIS`97, Austin, Texas, USA, October 8-10, 1997
(kj) (m. W.H. Mangione-Smith, B. Hutchins, D. Andrews, A. DeHon, C. Ebeling, O. Mencer, J. Morris, K. Palem, V. Prasanna, H. Spaanenburg): Current Issues in Configurable Computing Research; IEEE Computer, Vol. 30, No. 12, December 1997
(with Jürgen Becker): Hardware/Software Co-Design for data-driven Xputer-based Accelerators; Proc. of 10th Int. Conf. on VLSI Design (Theme: VLSI in Multimedia Applications), January 4-7, 1997, Hyderabad, India
(b) (with Michael Herz, Thomas Hoffmann, Ulrich Nageldinger): Using the KressArray for Configurable Computing; Proceedings of SPIE Vol. 3526, Conference on Configurable Computing: Technology and Applications, Boston, USA, November 2-3, 1998 <PDF>
(g) (with Michael Herz, Frank Gilbert): Designing for Xilinx XC6200 FPGAs; Proceedings of 8th International Workshop on Field-Programmable Logic and Applications, FPL’98, Tallinn, Estonia, August 31- September 3, 1998. Proceedings: Reiner W. Hartenstein, Adres Keevallik (Ed.), Lecture Notes in Computer Science 1482, Springer-Verlag, Germany, 1998 <PDF>
(g) (with Michael Herz, Thomas Hoffmann, Ulrich Nageldinger): Exploiting Contemporary Techniques in Reconfigurable Accelerators; Proc. 8th International Workshop on Field-Programmable Logic and Applications, FPL’98, Tallinn, Estonia, August 31- September 3, 1998. Proceedings: Reiner W. Hartenstein, Adres Keevallik (Ed.), Lecture Notes in Computer Science 1482, Springer-Verlag, Germany, 1998 <PDF>
(B) (Editor, together with Andres Keevallik): "Field-Programmable Logic and Applications: From FPGAs to Computing Paradigm"; Lecture Notes in Computer Science (LNCS No. 1482), Springer-Verlag Berlin/Heidelberg, 1998 - ISBN 3-540-64948-4
(g) (with Michael Herz, Thomas Hoffmann, Ulrich Nageldinger): On Reconfigurable Co-Processing Units; Proceedings of Reconfigurable Architectures Workshop (RAW98), held in conjunction with 12th International Parallel Processing Symposium (IPPS-98) and 9th Symposium on Parallel and Distributed Processing (SPDP-98), Orlando, Florida, USA, March 30,1998 Proceedings: Jose Rolim (Ed.): Parallel and Distributed Processing, Lecture Notes in Computer Science 1388, Springer-Verlag, Germany, 1998 <PDF>
(g) (with Jürgen Becker, Michael Herz, Ulrich Nageldinger): Parallelization in Co-Compilation for Configurable Accelerators; in proccedings of Asia and South Pacific Design Automation Conference, ASP-DAC’98, Yokohama, Japan, Feb. 10-13, 1998 <PDF>
(g) (with Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber): Interfacing the MoM-PDA to an Internet-based Development System; Proc. of 32th Anual Hawaii Int. Conf. on System Science (HICSS-32), January, Hawaii, USA, 1999 <PDF>
(g) (with Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber): XMDS: The Xputer Multimedia Development System; Proc. of 32th Anual Hawaii Int. Conf. on System Science (HICSS-32), January, Hawaii, USA, 1999 <PDF>
(g) (with M. Herz, T. Hoffmann, U. Nageldinger): Mapping Applications onto reconfigurable KressArrays; 9th International Workshop on Field Programmable Logic and Applications, FPL '99, Glasgow, UK, Aug.30-Sept.2, 1999 <PDF>
(g) (with M. Herz, T. Hoffmann, U. Nageldinger): An Internet Based Development Framework for Reconfigurable Computing; 9th International Workshop on Field Programmable Logic and Applications, FPL '99, Glasgow, UK, Aug.30-Sept.2, 1999 <PDF>
(B) 14. (Editor, together with Patrick Lysaght, James Irvine): "Field-Programmable Logic and Applications: 9th International Workshop, FPL'99, Glasgow, UK, August/September 1999, Proceedings"; Lecture Notes in Computer Science (LNCS No. 1673), Springer-Verlag Berlin/Heidelberg, 1999 - ISSN 0302-9743
(k) (zus. mit Prof. Dr. Josef Schmid): Erfordernisse der Wissensgesellschaft; Kaminsgespräch, Jahrestagung der Studiengeesellschaft für Mittelstandsfragen e.V., Innzell, 16. - 18. Oktober 1998; in: (Hrsg.) R. Strohmeier: Bilanz der Mittelstandspolitik, Wirtschaftswissenschaftliches Kolloquium, München 1999, ISBN 3-9803799-4-9 - translation of title -
(g) (with M. Herz, Th. Hoffmann, U. Nageldinger): KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures; 5th Asia and South Pacific Design Automation Conference 2000, ASP-DAC 2000, Pacifico Yokohama, Yokohama, Japan, January 25-28, 2000. <PDF>
(g) (with M.Herz, T.Hoffmann, U.Nageldinger): Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures; Proc. Field-Programmable Logic and Applications (FPL2000), Villach, Austria, August 2000; Lecture Notes in Computer Science, Springer-Verlag Berlin/Heidelberg, 2000 <PDF>
(kj) (eingeladener Beitrag): Der Mikroprozessor im nächsten Jahrtausend; Elektronik 49, 1, Jan. 11, 2000 - translation of title -
(B) (editor with H. Grünbacher): Field-Programmable Logic and Applications - The Roadmap to Reconfigurable Computing; Lecture Notes in Computer Science (LNCS No. 1896), Springer-Verlag Berlin/Heidelberg, 2000, ISBN 3-540-67899-9
(g) (with Th. Hoffmann, U. Nageldinger): Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures; Proc. PATMOS 2000, International Workshop - Power and Timing Modeling, Optimization and Simulation, Göttingen, Germany - September 13-15, 2000
(g) (with M. Herz, T. Hoffmann, U. Nageldinger): Synthesis and Domain-specific Optimization of KressArray-based Reconfigurable Computing Engines; 8th ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2000), Monterey, CA, USA, Feb. 9-11, 2000 <PDF>
(k) (invited embedded tutorial): Coarse Grain Reconfigurable Systems; Asian and South Pacific Design Automation Conference 2001 (ASP-DAC'01), Yokohama, Japan, Jan 30 - Feb. 2, 2001
(g) (embedded tutorial): A Decade of Research on Reconfigurable Architectures - a Visionary Retrospective; Proc. International Conference on Design Automation and Testing in Europe 2001 (DATE 2001), Exhibit and Congress Center, Munich, Germany, March 2001 - CiteULike -
(k) (invited keynote): Reconfigurable Computing: a New Business Model - and its Impact on SoC Design; DSD'2001 EUROMICRO SYMPOSIUM ON DIGITAL SYSTEMS DESIGN, Warzaw, Poland, Sept. 4 - 6, 2001
(k) (invited paper) "Reconfigurable Computing: the Roadmap to a New Business Model - and its Impact on SoC Design"; SBCCI 2001 - 15th Symposium on Integrated Circuits and Systems Design, Brasilia, DF, Brazil, September 10-15, 2001
(k) (invited paper) Reconfigurable Computing - Architectures and Methodologies for System-on-Chip; SoC technology seminar "Enabling Technologies for System-on-Chip Development"; Tampere, Finland, November 19-20, 2001,

(k) (invited keynote address) Configware / Software Co-Design: Be Prepared For the Next Revolution! 5th IEEE Workshop on Design & Diagnosis of Electronic Circuits & Systems (DDECS'02), Brno, Czech Republic, April 17 - 19, 2002 -
(k) (invited keynote address) Stream-based Computing - Antimatter of Informatics; First International Conf. on Intelligent Computing and Information Systems (ICICIS 2002), Cairo, Egypt, June 24-26, 2002.
(k) (invited course) Reconfigurable Computing; internatl workshop at CNRS, Paris, July 8 - 18, 2002
(k) (invited presentation (in German language)) Stream-based Computing: Antimaterie der Informatik; (Stream-based Computing: Antimatter of Informatics); 60th semester anniversary workshop, University of Dortmund, July 18. - 19, 2002
(g) (together with: M. Ayala-Rincón, R. Maya Neto, R. P. Jacobi, C. Llanos ): Applying ELAN Strategies in Simulating Processors over Simple Architectures; Proc. 2nd Int. Workshop on Reduction Strategies in Rewriting and Programming - WRS'02, pages 127-141, Copenhagen, Denmark, July 21, 2002 -- ppt. -- ps
(k) (invited keynote address) Reconfigurable Computing: urging a revision of basic CS curricula; Workshop on Logic and Synthesis for Programmable Devices - WLSPD2002, Las Vegas, USA, 6-8 August, 2002 -
(k) (invited keynote address) Disruptive Trends by Custom Compute Engines; 12th International Conference on Field Programmable Logic and Application FPL 2002, September 2 - 4, 2002, La Grande-Motte (Montpellier, France)
(k) (invited paper) Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
(k) (invited paper) (together wirh Michael Herz (Agilent Technologies), Miguel Miranda, Erik Brockmeyer (IMEC, Leuven, Belgium), Francky Catthoor (IMEC and K.U.Leuven, Belgium): Memory Organisation for Stream-based Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia <PDF>
(k) (panelist contribution): Panel on Embedded Architectures: Configurable, Re-configurable, or what? (panelists: Pierre Paulin, STMicro (moderator), Henk Corporaal, IMEC, Reiner Hartenstein, Univ. Kaiserslautern, Oz Levia, Improv Systems, Marco Pavesi, Italtel, Chris Rowen, Tensilica.); CASES 2002 (International Conference on Compilers, Architecture, and Syntheses for Embedded Systems), October 8-11, 2002, Grenoble, France, co-located with EMSOFT 2002 (Oct 7-9) -- ppt
(gj) (together with: M. Ayala-Rincón, R. Maya Neto, R. P. Jacobi, C. Llanos): Applying ELAN Strategies in Simulation Processors over Simple Architectures; (reprint from 2nd int'l Workshop on Reduction Strategies in Rewriting and Programming (WRS 2002); Copenhagen, Denmark, July 21, 2002) Electronic Notes in Theoretical Computer Science (ENTCS) 70/6; Elsevier Science Pubnlishers

(s) (together wirh M. Ayala-Rincón, R. P. Jacobi and C. Llanos, Designing Arithmetic Digital Circuits via Rewriting-Logic, - ps - Submitted 2002.
(s) (together with: M. Ayala-Rincón, R. Maya Neto, R. P. Jacobi, C. Llanos): Architectural Specification and Simulation Through Rewriting-Logic; -- ps - Submitted 2002.
(s) (together with J. Becker): Morphware and Configware and Morphware going Mainstream; -- pdf -- Submitted 2002
(k) Data-Stream-based Computing and Morphware; Joint 33rd Speedup and 19th PARS Workshop (Speedup / PARS 2003), Basel, Switzerland, March 2003
(s) (together with M. Ayala-Rincón, R. P. Jacobi, and C. Llanos): Modeling Reconfigurable Systolic Arrays for Computing Algebraic Operations via Rewriting-Logic, (, 1.4 MB; Pdf, 1.4 MB).
(k) (keynote address) Are we really ready for the Breakthrough?; 10th Reconfigurable Architectures Workshop, 2003 (RAW 2003), Nice, France, April 22, 2003
(k) (keynote address) A Mead-&-Conway-like Break-through is overdue; Dagstuhl Seminar Nº 03301, Dynamically Reconfigurable Architectures; Dagstuhl, Germany, 20.-25. 07. 2003,
(g) (together with M. Ayala-Rincón, R. B. Nogueira, R. P. Jacobi, and C. Llanos): Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic, (postscritp, X MB; PdfPDF, X MB). To appear in IEEE CS Press Proc. 16th Symposium on Integrated Circuits and System Design - SBCCI 03, Sã/o Paulo, Brasil, (Sep 8-11, 2003).
(g) (together with R. P. Jacobi, M. Ayala-Rincón and C. Llanos): Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing, (postscritp, X MB; Pdf, X MB). To appear in Forum on Specification and Design Languages - FDL 03, Frankfurt, Germany, (Sep 23-26, 2003).
(g) (together with M. Ayala-Rincón, R. Maya Neto, R. P. Jacobi, and C. Llanos): Architectural Specification, Exploration and Simulation Through Rewriting-Logic, (Postscript, 134 KB). In Colombian Journal of Computation, Vol 3(2):15 pages, 2003.
(kj) Reconfigurable Computing: Paradigmen-Wechsel erschüttern die Fundamente der Informatik; Anniversary Colloquium at Prof. Glesner's 60th Birthday; August 29, 2003, Darmstadt, Germany. TI Information Technology, 2003 (pdf)
(gj) (together with J. Becker): Configware and morphware going mainstream; Journal of Systems Architecture vol. Volume 49 , Issue 4-6 (September 2003), pp. 127-142, 2003.
(k): Data-Stream-Based Computing: Models and Architectural Resources; International Conference on Microelectronics, Devices and Materials (MIDEM 2003), Ptuj, Slovenia, Oct.1-3, 2003s
(k) (keynote address) The Digital Divide of Computing; Proc. 2004 ACM International Conference on Computing Frontiers (CF04); April, 14-18, 2004. Ischia, Italy,
(g) (together with: M. Ayala-Rincón, R. B. Nogueira, R.P. Jacobi, C. H. Llanos): Modeling and Prototyping Dynamically Reconfigurable Systems for Efficient Computation of Dynamic Programming Methods; ACM Proc. 17th Symposium on Integrated Circuits and System Design -CHIP ON THE REEFS - SBCCI'04, Porto de Galinhas, Pernambuco, Brazil, September 7-11, 2004, (postscript, Pdf)
(k) (keynote address - opening a new workshop series) Reconfigurable HPC: torpedoed by Deficits in Education ? Workshop on Reconfigurable Systems for HPC (RHPC); July 21, 2004, to be held in conjunction with HPC Asia 2004, 7th International Conference on High Performance Computing and Grid in Asia Pacific Region, Omiya Sonic City, Tokyo Area, Japan, July 20 - 22, 2004,
(g) (together with: R. Jacobi, M. Ayala Rincon, L. Carvalho, C. Llanos): Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming; 3rd Brasilian Workshop on Bioinformatics (wob 2004), Brasília, Distrito Federal, Brazil, October 20-22, 2004
(in preparation) (together with: M. Ayala-Rincón, R. P. Jacobi and C. Llanos, Designing Arithmetic Digital Circuits via Rewriting-Logic, (Postscript), 2004
(g) (together with: C. LLanos, R. P. Jacobi, M. Ayala-Rincón): A Dynamically Reconfigurable System for Space-Efficient Computation of the FFT, (ps, pdf). To appear in Soc. Mex. Comp. Proc. International Conference on Reconfigurable Computing and FPGAs 2004 (ReConFig'04), Colima, Mexico, Sept 20-21, 2004.
(submitted) (together with: M. Ayala-Rincón, C. Llanos, R. P. Jacobi): Prototyping Time and Space Efficient Computations of Algebraic Operations over Dynamically Reconfigurable Systems Modeled by Rewriting-Logic, (pdf), submitted 2004.
(k) (keynote address): Supercomputing goes Reconfigurable - About key issues and their impact on CS education;
Winter International Symposium on Information and Communication Technologies (WISICT 2005), Cape Town, South Africa, January 3 - 6, 2005
(k) (keynote address): Reconfigurable Computing (RC) being Mainstream: Torpedoed by Education; International Conference on Microelectronic Systems Education (MSE) conference, Anaheim, California, USA, 12-13 June 2005, in conjunction with DAC (Design Automation Conference) Anaheim, California, USA, 13 - 17 June 2005
(k) (keynote address): Programmable SoC progress stalled by unqualified programmers: CS curriculum upgrades enforceable or EE task force needed? - New EXploratory Technology (NEXT) Conference, Salo, Finland, October 3 - 4, 2005
(g) (together with C. Morra, J. Becker, M. Ayala-Rincon) FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations; 15th International Conference on Field-Programmable Logic and Applications, August 24 - 26, 2005, Tampoere, Finland, Proc. FPL 2005 (pdf)
(bj) (together with Bernard Widrow and Robert Hecht-Nielsen): 1917 Karl Steinbuch 2005; submitted for Nature
(kj) (together with Bernard Widrow and Robert Hecht-Nielsen): 1917 Karl Steinbuch 2005; IEEE Computational Intelligence Society Newsletter, August 2005 - pdf
(n) Obsolete Curriculum Recommendations; memorandum, August 2005
(n) Proposing a new Magazine; memorandum, September 2005 (pdf)
(gj) (together with R. Jacobi, M. Ayala-Rincón, L. Carvalho, C. Llanos:) Reconfigurable systems for sequence alignment and for general dynamic programming; journal GMR Genetics and Molecular Research 4 (3): 543-552 (2005) pdf
(i) KressArray: what is the achievement ? Generalization of the Systolic Array; memo, TU Kaiserslautern, 2005 (pdf)
(kj) (together with Bernard Widrow and Robert Hecht-Nielsen): 1917 Karl Steinbuch 2005; IEEE Computational Intelligence Society Magazine, to appear in the first issue, 2006
(kj) Morphware and Configware; in: A. Zomaya (editor): Handbook of Innovative Computing Paradigms; LNCS series, Springer Verlag Heidelberg/New York, 2006
(n) Overdue CS, CE and ECE Curriculum Innovations, memorandum, January 2006 - pdf
(kj) Configware für Supercomputing: Aufbruch zum Personal Supercomputer; PIK - Praxis der Informationsverarbeitung und Kommunikation, 2006 pdf
(gj) (together with M. Ayala-Rincón, And C. H. Llanos, And R. P. Jacobi): Prototyping Time and Space Efficient Computations of Algebraic Operations over Dynamically Reconfigurable Systems Modeled by Rewriting-Logic; accepted for ACM Transactions on Design Automation of Electronic Systems (TODAES), 2006 - pdf
(k) (keynote address) From Organic Computing to Reconfigurable Computing; The 8th Workshop on Parallel Systems and Algorithms (PASA 2006), March 16, 2006, Frankfurt/Main, Germany - in connection with the19th International Conference on Architecture of Computing Systems (ARCS 2006), March 13 - 16, 2006, Frankfurt/Main, Germany - pdf | ppt
(k) (keynote address) New horizons of very high performance computing (VHPC) - hurdles and chances; The 13th Reconfigurable Architectures Workshop (RAW 2006), Rhodos Island, Greece, April 25 - 26, 2006, pdf | ppt
(k) (keynote address) The Transdisciplinary Responsibility of CS Curricula; The 8th World Conference on Integrated Design & Process Technology (IDPT), June 25 - 29, 2006, San Diego, CA, USA - ppt | pdf
(k) Reconfigurable Supercomputing: Hurdles and Chances; International Supercomputer Conference (ICS 2006), June 28 - 30, 2006, Dresden, Germany (ppt | abstract: pdf)
(k) (keynote address) Why we need Reconfigurable Computing Education: Introduction; 1st International Workshop on Reconfigurable Computing Education (RCeducation), March 1, Karlsruhe,Germany (pdf | ppt
(wi) Higher Performance by less CPUs; HPCwire, in conjunction with ISC 2006, Dresden, Germany, June 27 - 30, 2006 http://www.supercomp.de/ (HPCwire)
(ai) Reconfigurable Supercomputing: Hurdles and Chances; International Supercomputer Conference (ICS 2006), June 28 - 30, 2006, Dresden, Germany (abstract)
(i) Generalization of the Systolic Array; memo, TU Kaiserslautern, 2006 (pdf)
(g) (together with C. Morra, R. Sackmann, J. Becker): Using Rewriting Logic To Generate Different Implementations Of Polynomial Approximations In Coarse-grained Architectures; Reconfigurable Communication-centric SoCs (ReCoSoc'06), July 3 - 5, 2006, Montpellier, France, (pdf)
(g) (together with C. Morra, M. Sackmann, S. Shukla, J. Becker): From Equation To Vhdl: Using Rewriting Logic For Automated Function Generation; 16th International Conference on Field-Programmable Logic and Applications, August 28 - 30, 2006, Madrid, Spain, Proc. FPL 2006 (pdf)
(kj) Basics of Reconfigurable Computing; in: J. Henkel, S. Parameswaran (editors): Embedded Computing - A Low Power Perspective, Springer-Verlag, 2007 (pdf) .
(k) (keynote) Reconfigurable computing means to brave the paradigm chasm; The HiPEAC Workshop on Reconfigurable Computing, Gent, Belgium, January 28, 2007
(ai) Compilation Techniques promising to bridge the Software / Configware Chasm The Computer Engineering Colloquium, TU Delft, Holland, February 22, 2007
(ai) Computing at the Crossroads: our Skills becoming Obsolete ? Kolloquium, International University in Germany at Bruchsal, March 20, 2007
(gj) Reconfigurable Supercomputing - Aktuelles Schlagwort; eingereicht beim GI Informatik-Spektrum (pdf)
(k) (opening keynoteaddress) Reconfigurable Computing and the von Neumann syndrome; The 7th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), June 11 - 14, 2007, Hangzhou, China
(k) (kj) (invited paper, invited book chapter): The von Neumann Syndrome; Stamatis Vassisliadis Memorial Symposium, Sep 28, 2007, Delft, The Netherlands
(k) (invited presentation) The Neumann Syndrome calls for a revolution; First InternationalWorkshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA'07), in conjunction with Supercomputing 2007 (SC07), 10.-17. Nov. 2007,
Reno, Nevada, USA,
(k) (invited presentation) HPC, SMEs and the price of oil; FET (Future and Emerging Technologies) Workshop on Massive ICT Systems (preparing call for funding in 2009-2010), Kommission of the European Union, November 27, 007, Brussels, Belgium
(i) Reconfigurable Supercomputing - Aktuelles Schlagwort; eingereicht beim GI Informatik-Spektrum


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