Xputer Laboratory at Kaiserslautern University 

Xputer-related Quotation Index 

Computer Structures Group (CSG) 
Prof. Dr.-Ing. Reiner W. Hartenstein

http://www.fpl.uni-kl.de/xputer/reference_list/quotation_index.html

 

 

last update in 1998


 
[103]                Keyword:     Quoted in:          
[102]               Keyword:      Quoted in:          
[101]

 

Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann: An Internet Based Development Framework for Reconfigurable Computing                           
Keyword:
Quoted in:          
[100]

 

Michael Herz , Thomas Hoffmann , Ulrich Nageldinger , Christian Schreiber: Interfacing the MoM-PDA to an Internet-based Development System; Proc. HICSS-32                                                      Herz list: 
Keyword:
Quoted in:          
[99]

 

Reiner Hartenstein , Michael Herz , Thomas Hoffmann , Ulrich Nageldinger: Using the Kress-Array for Reconfigurable Computing; Proc. SPIE                 
Keyword:
Quoted in:          
[98]

 

R Hartenstein, J Becker, M Herz, U. Nageldinger: A Novel Universal Sequencer Hardware; ITG/GI-Fachtagung Architektur von Rechensystemen, ARCS '97, Rostock, September 1997,         
Keyword:
Quoted in:          
[97]

 

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger: On Reconfigurable Co-processing Units; Proc.Reconfigurable Architectures Workshop (RAW98), Orlando, Florida, March 1998. Herz:       
Keyword:
Quoted in:     

Hatem M. El-boghdadi, Ramachandran Vaidyanathan, Jerry L. Trahan, Suresh Rai: On the Communication Capability of the Self-Reconfigurable Gate Array; 9th Reconfigurable Architectures Workshop; Proc. Int. Parallel and Distrib. Proc. Symp , 2002    

[96]

 

R. W. Hartenstein , J. Becker , M. Herz , U. Nageldinger: An Embedded Accelerator for Real World Computing; Proceedings of IFIP International Conference on Very Large Scale Integration, VLSI’97, Gramado, UFRGS, Brasil, August 26 - 29, 1997       
Keyword:
Quoted in:          
[95]

 

R. W. Hartenstein , J. Becker , M. Herz , U. Nageldinger: Data Scheduling in Hardware/Software Co-Design for field-programmable Accelerators; Proceedings of 7th International Workshop on Field Programmable Logic, FPL‘97, London, UK, September 1-3, 1997       
Keyword:
Quoted in:          
[94]

 

R. W. Hartenstein , M. Herz , T. Hoffmann , U. Nageldinger: Exploiting Contemporary Memory Techniques; 8th International Workshop on Field Programmable Logic and Applications, FPL’98, Tallinn. Estonia
Keyword:
Quoted in:          

[93]

 

Reiner W. Hartenstein, Viktor K. Prasanna, editors, Reconfigurable Architectures - High Performance by Configware, ITpress Verlag, Germany 1997
Keyword:
Quoted in:          
Kiran Bondalapati and Viktor K. Prasanna: Mapping Loops onto Reconfigurable Architectures; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[92] Reiner W. Hartenstein, Andreas Keevallik, editors, Field-Programmable Logic and Applications - From FPGAs to Computing Paradigm, Springer-Verlag, Germany 1998, FPL ´98, Lecture Notes in Computer Science 1482
Keyword:
Quoted in:          
Tero Rissa, Tommi Mäkeläinen, Jarkko Niitty and Jouni Siirtola, editors: Fast Prototyping Using System Emulators; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[91] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, pp. 337 - 345, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:                    
Andrej Trost, Andrej Zemva, Baldomir Zajc: Programmable Prototyping System for Image Processing; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[90] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:         
Wayne Luk and Steve McKeever: Pebble: A Language for Parametrised and Reconfigurable Hardware Design; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[89] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:          
Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[88] Reiner W. Hartenstein, Andreas Keevallik, editors, Field-Programmable Logic and Applications - From FPGAs to Computing Paradigm, Springer-Verlag, Germany 1998, FPL ´98, Lecture Notes in Computer Science 1482
Keyword:
Quoted in:          
Gordon Brebner: Field-Programmable Logic: Catalyst for New Computing Paradigms; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[87] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:          
N. Shirazi, W. Luk, P.Y.K. Cheung: Run-Time Management of Dynamically Reconfigurable Designs; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[86] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, pp. 136- 145, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:          
Marco Platzner and Giovanni De Micheli: Acceleration of Satisfiability Algorithms by Reconfigurable Hardware; 8th International Workshop, FPL ´9Quoted in:8; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998 
[85] R.W. Hartenstein, M.Z. Servit, editors, Field-Programmable Logic - Architectures, Synthesis and Applications, Springer-Verlag, Germany 1994, pp. 11- 22, FPL ´94, Lecture Notes in Computer Science 849
Keyword:
Quoted in:           
M. Renovell, J.M. Portal, J. Figueras, Y. Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logic Modules; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[84] Reiner W. Hartenstein, Andreas Keevallik, editors, Field-Programmable Logic and Applications - From FPGAs to Computing Paradigm, Springer-Verlag, Germany 1998, FPL ´98, Lecture Notes in Computer Science 1482
Keyword:
Quoted in:          
W. Luk, P. Andreou, A. Derbyshire, F. Dupont-De-Dinechin, J. Rice, N. Shirazi and D. Siganos: A Reconfigurable Engine for Real-Time Video Processing; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[83] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, pp. 327 - 336, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:            
Adam Donlin: Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[82] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:           
Dinesh Bhatia, Parivallal Kannan, Kuldeep S. Sinha, Karthikeya M. Gajjala Purna: REACT: Reactive Environment for Runtime Reconfiguration; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[81] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:          
W. Luk, P. Andreou, A. Derbyshire, F. Dupunt-De-Dinechin, J. Rice, N. Shirazi and D. Siganos: A Reconfigurable Engine for Real-Time Video Processing; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[80] R.W. Hartenstein, M. Glesner, editors, Field-Programmable Logic - Smart Applications, New Paradigms and Compilers, Springer-Verlag, Germany 1996, pp. 197 - 306, FPL ´96, Lecture Notes in Computer Science 1142
Keyword:
Quoted in:          
Gordon McGregor, David Robinson and Patrick Lysaght: A Hardware/Software Co-design Environment for Reconfigurable Logic Systems; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[79] Herbert Grünbacher and Reiner W. Hartenstein, editors, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, pages 152 - 162, 1992. Proceedings of the 2nd International Workshop on Field-Programmable Logic and Applications, FPL 92. Lecture Notes in Computer Science 705
Keyword:
Quoted in:         
Steven A. Guccione: WebScope: A Circuit Debug Tool; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998

[78] R. Kress, R.W. Hartenstein, U. Nageldinger, An Operating System for Custom Computing Machines based on the Xputer Paradigm. In 7th International Workshop on Field-Programmable Logic and Applications, pages 304 - 313, Sept. 1997
Keyword:
Quoted in:    
Kiran Bondalapati and Viktor K. Prasanna: Mapping Loops onto Reconfigurable Architectures; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[77] R.W. Hartenstein, et al., “A Reconfigurable Data-Driven ALU for Xputers”, IEEE Workshop on FPGAs for Custom Computing Machines, FCCM ´94, Napa, CA, April 1994
Keyword:
Quoted in:           
B. Radunovic, V. Milutinovic: A Survey of Reconfigurable Computing Architectures; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[76] R.W. Hartenstein, et al., “A Novel Sequencer Hardware for Application Specific Computing”, ASAP ´97, Zurich, Switzerland, July 1997
Keyword:
Quoted in:     
B. Radunovic, V. Milutinovic: A Survey of Reconfigurable Computing Architectures; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[75] R.W. Hartenstein, “The Microprocessor is no more General Purpose: why Future Reconfigurable Platform will win”, Proceedings of the International Conference on Innovative Systems in Silicon, October 1997
Keyword:
Quoted in:  
B. Radunovic, V. Milutinovic: A Survey of Reconfigurable Computing Architectures; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[74] R.W. Hartenstein, R. Kress, H. Reinig, “A Scalable, Parallel and Reconfigurable Datapath Architecture”, 6th Int. Symposium on IC Technology, Systems & Applications, sept. 1995.
Keyword:
Quoted in:   
Andreas Dandalis and Viktor K. Prasanna: Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[73] R.W. Hartenstein, J. Becker, R. Kress, “Custom Computing Machines vs. Hardware/Software Co-Design: From a Globalized Point of View”, 6th Int. Workshop on Field Programmable Logic and Appl., FPL ´96, Darmstadt, Sept. 1996, Lecture Notes in Computer Science 1142, Springer 1996
Keyword:
Quoted in: 
Christian Siemers and Dietmar P.F. Möller: The >S<puter: Introducing a Novel Concept for Dispatching Instructions Using Reconfigurable Hardware; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[72] R.W. Hartenstein, et al.: A Novel Machine Paradigm to Accelerate Scientific Computing; Special issue on Scientific Computing of Computer Science and Informatics Journal, Computer Soc. of India, 1996
Keyword:
Quoted in:       
Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[71] R.W. Hartenstein, et al.: A Reconfigurable Machine for Applications in Image and Video Compression; Europ. Symp. on Advanced Networks and Services, Conf. on Compression Technologies & Standards for Image & Video Compression, Amsterdam, The Netherlands, March 20 - 24, 1995.
Keyword:
Quoted in:         
Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[70] R.W. Hartenstein et al.: High Performance Computing Using a Reconfigurable Accelerator; Proc. of Workshop on High Performance Computing , Motreal, Canada, July 1995.
Keyword:
Quoted in:           
Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[69] R.W. Hartenstein: An Overview on Custom Computing Machines; Workshop on Design Methodologies for Microelectronics, Invited Paper, Smolenice Castle, Slovakia, Sept. 1995
Keyword:
Quoted in:           
Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[68] Hartenstein, Becker and Kress, “Custom Computing Machines vs. Hardware/Software Co-Design: From a Globalized Point of View”, Proc. 6th International Workshop on Field-Programmable Logig and Applications, Springer LNCS 1142, pp.65-76
Keyword:
Quoted in:          
Gordon Brebner: Field-Programmable Logic: Catalyst for New Computing Paradigms; 8th International Workshop, FPL ´98; Tallin, Estonia, August 31 - September 3, 1998, Lecture Notes in Computer Science 1482, Springer 1998
[67] S.H.-M- Ludwig. The design of a coprocessor board using Xilinx´s XC6200 FPGA - An experience reprt. In R.W. Hartenstein and M. Glesner, editors, Field Programmable Logic: Smart Applications, New Paradigms and Compilers, (FPL ´96 Proceedings), LNCS 1142, pages 77-85; Springer-Verlag, 1996.
Keyword:
Quoted in:         
Milan Vasilko and David Long: RIFLE-62: A Flexible Environment for Trototyping Dynamically Reconfigurable Systems; Proceedings, Ninth International Workshop on Rapid System Prototyping, June 3-6, 1998.
[66] A. Ast, R. W. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Data-procedural Languages for FPL-based Machines; 4rd Int. Workshop On Field Programmable Logic And Applications, FPL’94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994 
Keyword:
Quoted in:           
H. Kropp, C. Reuter, P. Pirsch: The Video and Image Processing Emulation System VIPES, Ninth International Workshop on Rapid System Prototyping, June 3-6, 1998.
[65] R.W. Hartenstein and M. Glesner, editors, Field Programmable Logic: Smart Applications, New Paradigms and Compilers, (FPL ´96 Proceedings), LNCS 1142; Springer-Verlag, 1996.
Keyword:
Quoted in:         
K.M.G. Purna, D. Bhatia: Emulating Large Designs on Small Reconfigurable Hardware, Ninth International Workshop on Rapid System Prototyping, June 3-6, 1998.
[64] R. W. Hartenstein, J. Becker, R. Kress; „Custom Computing Machines vs. Hardware-Software Codesign: From a Globalized Pint of View“; Proc. of the 1996 Intl. Workshop on Field Programmable Logic and Applications.
Keyword: Hardware/Software Codesign
Quoted in:           
Ferran Lisa-Mingo, Jordi Carrabina: A Library of Memory Controllers for an Image Processing Prototyping System; Proceedings, Ninth International Workshop on Rapid System Prototyping, June 3-6, 1998.
[63] R. W. Hartenstein, J. Becker and R. Kress, „A Profiling-driven Hardware/Software Partitioning of High-Level Language Specifications“, IFIP International Workshop on Logic and Architecture Synthesis, Grenoble, France, 1995.
Keyword: Hardware/Software Codesign
Quoted in:         
Karam S. Chatah and Ranga Vemuri: Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns; Proceedings, Ninth International Workshop on Rapid System Prototyping, June 3-6, 1998.
[62] J. Becker, R. W. Hartenstein, M. Herz and U. Nageldinger. Parallelization in co-compilation for configurable accelerators. In Proc. of the Asia and South Pacific Designe Automation Conference, pages 23-33, 2 1998.
Keyword:
Quoted in:           
Hideyuki Ito, Kiyoshi Oguri, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa: The Plastic Cell Architecture for Dynamic Reconfigurable Computing; Proceedings, Ninth International Workshop on Rapid System Prototyping, June 3-6, 1998.
[61] R. W. Hartenstein, et al.: A Novel Machine Paradigm to Accelerate Scientific Computing; Special issue on Scientific Computing of Computer Science an Informatics Journal, Computer Society of India, 1996.
Keyword:
Quoted in:           
J. Becker, F.-M. Renner, M. Glesner: Perspectives of Reconfigurable Computing in Education; Microelectronics Education, Proceeding of the 2nd European Workshop held in Noordwjikerhout, The Netherlands, 14-15 May 1998.
[60] R.W. Hartenstein, et al.: A Reconfigurable Machine for Applications in Image and Video Compression; Europ. Symp. on Advanced Networks and Services, Conf. on Compression Technologies & Standards for Image & Video Compression, Amsterdam, The Netherlands, March 20-24, 1995.
Keyword:
Quoted in:           
J. Becker, F.-M. Renner, M. Glesner: Perspectives of Reconfigurable Computing in Education; Microelectronics Education, Proceeding of the 2nd European Workshop held in Noordwjikerhout, The Netherlands, 14-15 May 1998.
[59] R.W. Hartenstein, R. Kress, H. Reinig: High-Performance Computing Using a Reconfigurable Accelerator; Proc of Workshop on High Performance Computing, Montreal, Canada, 1995.
Keyword:
Quoted in:           
J. Becker, F.-M. Renner, M. Glesner: Perspectives of Reconfigurable Computing in Education; Microelectronics Education, Proceeding of the 2nd European Workshop held in Noordwjikerhout, The Netherlands, 14-15 May 1998.
[58] R.W. Hartenstein, M. Glesner: 6th Int´l Workshop on Field-Programmable Logic: Smart Applications, New Paradigms and Compilers (FPL ´96); Sep. 1996, Darmstadt, Germany.
Keyword:
Quoted in:  
J. Becker, F.-M. Renner, M. Glesner: Perspectives of Reconfigurable Computing in Education; Microelectronics Education, Proceeding of the 2nd European Workshop held in Noordwjikerhout, The Netherlands, 14-15 May 1998.
[57] R. W. Hartenstein et al: Two-Level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine: Proc. of the 4th Int. Workshop on Hardware/Software Codesign, 1996.
Keyword: automatic hardware/software partitioning
Quoted in: 
T. Hollstein, J. Becker, A. Kirschbaum, M. Glesner: HiPART: A New Smi-Interactive HW-/SW Partitioning Approach with Fast Debugging for Real-Time Embedded Systems; 6th Int. Workshop on Hardware/Software Codesign, March 15-18, 1998.
[56] R. W. Hartenstein et al: A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. IEEE 1997 HICSS-30, Wailea, Maui, Hawaii, January 1997.
Keyword: hardware/software partitioning
Quoted in: 
M. Eisenring, J. Teich: Domain-Specific Interface Generation form Dataflow Specifications; 6th Int. Workshop on Hardware/Software Codesign, March 15-18, 1998.
[55] Reiner W. Hartenstein, Jürgen Becker, et al.: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL'96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996
Keyword: Custom Computing Machines
Quoted in:          
C. Siemers, D. P. F. Möller, S. Roth: Die (zukuenftige) Bedeutung von Hardware-Software Co-Design fuer Embedded Systeme; Proceedings of Embedded Intelligence '98, Sindelfingen, Feb. 1998
[54] R. W. Hartenstein, J. Becker, R. Kress: Custom Computing Machines vs. Hardware/Software Co-Design: From a Globalized Point of View; 6th Int. Workshop on Field-Programmable Logic and Applications, FPL’96, Darmstadt, September 1996.
Keywords: (1) Custom Computing Machines, (2) Xputer
Quoted in:               
C. Siemers: Rechnerarchitekturen in Bewegung; Elektronik, February 17. 1998.
[53] R. W. Hartenstein, J. Becker, R. Kress, H. Reinig: High-Performance Computing Using a Reconfigurable Accelerator. CPE Journal, Special Issue on Concurrency: Practice and Experience. John Wiley & Sons Ltd., 1996
Keywords: (1) Custom Computing Machines, (2) Xputer
Quoted in:            
C. Siemers: Rechnerarchitekturen in Bewegung; Elektronik, February 17. 1998.
[52] R. W. Hartenstein et. al.: A New FPGA Architecture for Word-Oriented Datapaths; Proceedings of FPL’94, Springer LNCS 849, September 1994.
Keyword: KressArray
Quoted in:           
T. Miyazaki: Reconfigurable Systems: A Survey; ASP-DAC’98, February 10-13, 1998.
[51] R. Hartenstein,A. Hierschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW, Future Generation Computer Systems 7 91/92, p. 181-198, North Holland
Quoted in: 
C. Siemers, D. P. F. Möller: The >S<puter: A Novel Microarchitecturemodel for Execution inside Superscalar and VLIW Processors Using Reconfigurable Hardware; in John Morris (Ed.): Computer Architecture 98; Proceedings of the 3rd Australasian Computer Architecture Conference ACAC'98, Perth, Feb. 1998, p.169-178. Springer Verlag, Singapore, 1998.
[50] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1996
Quoted in:          
C. Siemers, D. P. F. Möller: The >S<puter: A Novel Microarchitecturemodel for Execution inside Superscalar and VLIW Processors Using Reconfigurable Hardware; in John Morris (Ed.): Computer Architecture 98; Proceedings of the 3rd Australasian Computer Architecture Conference ACAC'98, Perth, Feb. 1998, p.169-178. Springer Verlag, Singapore, 1998.
[49] Reiner W. Hartenstein, Jürgen Becker, et al.: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL'96,Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996
Quoted in:          
C. Siemers, D. P. F. Möller: The >S<puter: A Novel Microarchitecturemodel for Execution inside Superscalar and VLIW Processors Using Reconfigurable Hardware; in John Morris (Ed.): Computer Architecture 98; Proceedings of the 3rd Australasian Computer Architecture Conference ACAC'98, Perth, Feb. 1998, p.169-178. Springer Verlag, Singapore, 1998.
[48] A. Ast, R. W. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Data-procedural Languages for FPL-based Machines; 4rd Int. Workshop On Field Programmable Logic And Applications, FPL’94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 199 
Quoted in:         
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 19984
[47] Reiner W. Hartenstein, Karin Schmidt: Performance Evaluation in Xputer-based Accelerators; Proc. of 4th Reconfigurable Architectures Workshop RAW-97, in conjunction with 11th Int’l. Parallel Processing Symposium, IPPS’97, Geneva, Switzerland, April 1-5,1997
Quoted in:        
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[46] Reiner W. Hartenstein: A Two-level Co-Design Framework for data-driven Xputer-based Accelerators; Proc. of 30th Annual Hawaii Int. Conf. on System Science (HICSS-30), January 7-10, Wailea, Maui, Hawaii, USA, 1997
Quoted in:
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[45] Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. of IEEE 1996 Int’l. Conference on Innovative Systems in Silicon; Austin, Texas, USA, October 9-11, 1996
Quoted in:        
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[44] Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger: A Parallelizing Programming Environment for Embedded Xputer-based Accelerators; High Performance Computing Symposium ‘96, Ottawa, Canada, June 1996
Quoted in:        
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[43] R. W. Hartenstein, R. Kress: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; Asia and South Pacific Design Automation Conference, ASP-DAC’95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug. 29 - Sept. 1, 1995
Quoted in:        
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[42] R. Hartenstein, A. Hierschbiel, K. Schmidt, M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW, Future Generation Computer Systems 7 91/92, p. 181-198, North Holland
Quoted in:
J. Becker, K. Schmidt: Automatic Parallelism Exploitation for FPL-based Accelerators; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[41] Reiner W. Hartenstein, Jürgen Becker: A Two-level Co-Design Framework for data-driven Xputer-based Accelerators; Proc. of 30th Annual Hawaii Int. Conf. on System Science (HICSS-30), January 7-10, Wailea, Maui, Hawaii, USA, 1997
Quoted in:         
M. Eisenring, J. Teich: Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[40] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL’96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996
Quoted in:         
M. Eisenring, J. Teich: Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[39] Reiner W. Hartenstein (opening key note): Custom Computing Machines - An Overview; Workshop on Design Methodologies for Microelectronics, Smolenice Castle, Slovakia, September 1995
Keyword: Custom Computing Machines
Quoted in:           
A. Postula, D. Abramson, Z. Fang, P. Logothetis: A Comparison of HIgh Level Synthesis and Register Transfer Level Design Techniques for Custom Computing; Proc. of Software Technology Track of the 31st Hawaii International Conference on System Sciences (HICSS-31), Big Island of Hawaii, January 6-9, 1998
[38] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL’96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996
Keyword:
Quoted in:
O. Yamamoto, Y. Shibata, H. Kurosawa, H. Amano: A reconfigurable Markow chain simulator for analysis of parallel systems; Proceedings of the International Conference on Innovative Systems in Silicon, ISIS'97, Austin, Texas, USA, October 8-10, 1997
[37] R. Hartenstein,A. Hierschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW, Future Generation Computer Systems 7 91/92, p. 181-198, North Holland
Keywords: (1,2) Xputer, (3) partitioning
Quoted in:         
C. Siemers, D. P. F. Möller: The >S<puter: A Novel Microarchitecturemodel for the Execution of Instructions inside Processors; in Xu De, K.-E. Grosspietsch, Ch. Steigner (Eds.): Proceedings of the Second Sino-German Workshop on Advanced Parallel Processing Technologies APPT'97, Koblenz, September 199, p. 75-81. Foelbach Verlag, Koblenz 1997.
[36] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1996
Keywords: (1,2) Xputer, (3) partitioning
Quoted in:          
C. Siemers, D. P. F. Möller: The >S<puter: A Novel Microarchitecturemodel for the Execution of Instructions inside Processors; in Xu De, K.-E. Grosspietsch, Ch. Steigner (Eds.): Proceedings of the Second Sino-German Workshop on Advanced Parallel Processing Technologies APPT'97, Koblenz, September 199, p. 75-81. Foelbach Verlag, Koblenz 1997.
[35] R. Hartenstein,A. Hierschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW, Future Generation Computer Systems 7 91/92, p. 181-198, North Holland
Keyword: (1,2) Xputer, (3) partitioning
Quoted in:      
C. Siemers, D. P. F. Möller: Der >S<puter: Ein dynamisch rekonfigurierbares Mikrorechnermodell zur Erreichung des maximalen Instruktionsparallelitätsgrades; in Proceedings of Fachtagung Architekturen von Rechensystemen ARCS'97, Rostock, Germany, September 8-11, 1997
[34] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1996
Keyword: (1,2) Xputer, (3) partitioning
Quoted in:          
C. Siemers, D. P. F. Möller: Der >S<puter: Ein dynamisch rekonfigurierbares Mikrorechnermodell zur Erreichung des maximalen Instruktionsparallelitätsgrades; in Proceedings of Fachtagung Architekturen von Rechensystemen ARCS'97, Rostock, Germany, September 8-11, 1997
[33] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL’96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996
Quoted in:          
B. Kahne, P. Athanas: Stream Synthesis for a Wormhole Run-Time Reconfigurable Platform; in Proceedings of 7th International Workshop on Field Programmable Logic, FPL‘97, London, UK, September 1-3, 1997
[32] R. W. Hartenstein, M. Riedmüller, K. Schmitt, M. Weber: A Novel Asic Design Approach Based on a New Machine Paradigm; Special Issue of IEEE Journal of Solid State Circuits on ESSCIRC´90, July 1991 
Keyword: reconfigurable logic coprocessor
Quoted in:          
E. Lechner, S. A. Guccione: the Java Environment for Reconfigurable Computing; in Proceedings of 7th International Workshop on Field Programmable Logic, FPL‘97, London, UK, September 1-3, 1997
[31] H. Grünbacher, R. W. Hartenstein: Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping. Springer Verlag, Berlin, 1992
Keyword: (1,2,3) FPGAs, (4) Co-Design, Xputers
Quoted in:          
K. Schlüter: Softe Hardware; PC Magazin DOS, May 1997
[30] R. W. Hartenstein, M. Z. Servit: Field-Programmable Logic. Architectures, Synthesis and Applications. Springer Verlag, Berlin, 1994.
Keyword: (1,2,3) FPGAs, (4) Co-Design, Xputers
Quoted in:         
K. Schlüter: Softe Hardware; PC Magazin DOS, May 1997
[29] R. W. Hartenstein: Field-Programmable Logic. Smart Applications, New Paradigma and Compilers. Springer Verlag, Berlin, 1996.
Keyword: (1,2,3) FPGAs, (4) Co-Design, Xputers
Quoted in:         
K. Schlüter: Softe Hardware; PC Magazin DOS, May 1997
[28] R. W. Hartenstein, J. Becker: A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. IEEE 1997 HICSS-30, Wailea, Maui, Hawaii, January 1997.
Keyword: (1,2,3) FPGAs, (4) Co-Design, Xputers
Quoted in:         
K. Schlüter: Softe Hardware; PC Magazin DOS, May 1997
[27] Ph.D. Thesis Kress
Quoted in:           
T. Ewing, J. W. Rosenblit: Simulation-Based Verification in HW/SW Codesign: An FPGA Approach; in Proc. of 4th Reconfigurable Architectures Workshop RAW-97, in conjunction with 11th Int’l. Parallel Processing Symposium, IPPS’97, Geneva, Switzerland, April 1-5,1997
[26] R.W. Hartenstein, A.G. Hirschbiel, M.Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan’90- International Conference memorating the 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990
Quoted in:         
M. A. Perkowski, L. Jozwiak, D. Foote: Architecture of a Programmable FPGA Coprocessor for Constructive Induction Approach to Machine Learning and other Discrete Optimization Problems; in Proc. of 4th Reconfigurable Architectures Workshop RAW-97, in conjunction with 11th Int’l. Parallel Processing Symposium, IPPS’97, Geneva, Switzerland, April 1-5,1997
[25] R. Hartenstein, J Becker, R. Kress: CoDe-X: Two-Level Partitioning for image processing algorithms for the parallel map-oriented machine; 4th Int’l. Workshop on Hardware/Software Co-Design CODES/CASHE 96, pp. 77-84, Pittsburgh, USA, March 1996
Keyword: Functional Partitioners among software and reconfigurable accelerators
Quoted in:           
F. Vahid: Modifying Min-Cut for Hardware and Software Functional Partitioning; submitted for 5th Int’l. Workshop on Hardware/Software Co-Design CODES/CASHE 97, March 24-26, Braunschweig, Germany, 1997
[24] R.W. Hartenstein, A.G. Hirschbiel, K. Schmidt, M. Weber: A Novel ASIC Design Approach based on a New Machine Paradigm; IEEE Journal of Solid-State Circuits, vol. 26, no. 7, pp. 975-989, July 1991 
Keyword: Hardware-Software System Architectures
Quoted in:        
R. Gupta (University of California—Irvine): Tutorial on HW/SW Codesign; 10th Int’l. Conf. on VLSI Design, Hyderabad, India, January 4-7, 1997
[23] R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London, 1989 
Keyword: Hardware-Software System Architectures
Quoted in:        
R. Gupta (University of California—Irvine): Tutorial on HW/SW Codesign; 10th Int’l. Conf. on VLSI Design, Hyderabad, India, January 4-7, 1997
[22] Reiner W. Hartenstein et. al.: KARL-III Language Reference Manual, Universität Kaiserslautern, Fachbereich Informatik, 1986; sowie R.W. Hartenstein and W. Ryba: Partitionierungsschemata für Rechnerstrukturen. In Design Methodologies for VLSI and Computer Architecture North-Holland, 1988.
Keyword:
Quoted in:           
Walter H. Burkhardt and Stefan Rust: Bericht Nr. 1996/11, Integrated Software / Hardware Development System; Universität Stuttgart, Institut für Informatik, Breitwiesenstraße 20, D-70565 Stuttgart, Germany.
[21] Reiner W. Hartenstein: Hardware/Software Co-Design; aktuelles Schlagwort; GI Informatik-Spektrum 18: p. 286-287, Springer-Verlag, Okt. 1995
Keyword: strukturaler Programmierung
Quoted in:         
C. Siemers: Paradigmenwechsel in Sicht?; Design & Elektronik 19, 17. Sept. 1996
[20] R. Hartenstein, J Becker, R. Kress, H. Reinig: CoDe-X: A Novel Two-Level Hardware/Software Co-Design Framework; VLSI Design´96, Bangalore, India, January 1996
Keyword: Codesign system targeting to set of general microprocessors and FPGAs
Quoted in:         
K. Tammemäe, M. O´Nils, A. Hemani: Flexible codesign target architecture for early prototyping of CMIST systems; submitted for FPL 96, Darmstadt, Germany, 1996
[19]

MoM Xputer Prototype: referencing the Kaiserslautern CSG publications listing

Keyword: FPGA-based Custom Computing Machine

Quoted in:

S. A. Guccione: List of FPGA-based Custom Computing Machines;  last update: 26 August, 1996

[18] A. Ast, J. Becker, R. W. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Data-procedural Languages for FPL-based Machines; 4rd Int. Workshop On Field Programmable Logic And Applications, FPL’94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994            
Keyword: data-procedural languages
Quoted in:          
B. Fawcett, J. Watson: Reconfigurable Processing with Field Programmable Gate Arrays; Proc. of Int’l. Conf. on Application Specific Systems, Architectures and Processors (ASAP96), pp. 293-302, Chicago, IL, 1996
[17] Reiner W. Hartenstein: Custom Computing Machines; aktuelles Schlagwort; GI Informatik-Spektrum 18: p. 228-229, Springer-Verlag, Oktober 1995
Keyword: Application Specific Processors
Quoted in:          
Adam Postula, David Abramson, Paul Logothethis Univ. of Queensland, Brisbane, Australia; Griffith Univ., Brisbane, Australia): Synthesis for Prototyping of Application Specific Processors; Proc. of 3rd Asia Pacific Conference on Hardware Description Languages (APCHDL´96), Bangalore, India, Jan. 1996
[16] Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt: A Two-Level Hardware/Software Co-Design Framework for Automatic Accelerator Generation; Workshop on Design Methodologies for Microelectronics, Smolenice Castle, Slovakia, September 1995 
Keyword: Application Specific Processors
Quoted in:         
Adam Postula, David Abramson, Paul Logothethis Univ. of Queensland, Brisbane, Australia; Griffith Univ., Brisbane, Australia): Synthesis for Prototyping of Application Specific Processors; Proc. of 3rd Asia Pacific Conference on Hardware Description Languages (APCHDL´96), Bangalore, India, Jan. 1996
[15] Reiner Hartenstein, Hardware/Software Codesign; Informatik Spektrum Band 18 Heft 5, Oktober 1995, pp 286-287.
Keyword: Hardware/Software Codesign
Quoted in:         
Universität Stuttgart, Fakultät Informatik; Prüfer: Prof. Dr.-Ing. U.G. Baitinger, Betreuer: Dipl.-Inform. Patricia Sagmeister; Beginn am: 26.2.1996, Beendet am: 26.8.1996; CR-Klassifikation D.1.5, D.2.2, D.2.10; Diplomarbeit Nr. 1392; Stefan Zink: Entwicklung und Implementierung eines Spezifikationswerkzeugs für komplexe heterogene Systeme; Institut füe Parallele und Verteilte Hochleistungsrechner, Breitwiesenstraße 20-22, D-70565 Stuttgart.
[14] R.W. Hartenstein, A.G. Hirschbiel, K. Schmidt, M. Weber: A Novel ASIC Design Approach based on a New Machine Paradigm; European Solid-State Circuits Conference `90, Grenoble, Frankreich 
Keyword: data-driven architectures for implementing systolic algorithms
Quoted in:            
R. Gupta (University of Illinois—Urbana): Co-Synthesis of Hardware and Software for Digital Embedded Systems; Kluwer Academic Publ., Boston, Dordrecht, London, 1995
[13] R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London, 1989 
Keyword: architectural principles in prototyping implementations of non-systolic algorithms (1 Referenz)
Quoted in:         
R. Gupta (University of Illinois—Urbana): Co-Synthesis of Hardware and Software for Digital Embedded Systems; Kluwer Academic Publ., Boston, Dordrecht, London, 1995
[12] R.W. Hartenstein, A.G. Hirschbiel, K. Schmidt, M. Weber: A Novel ASIC Design Approach based on a New Machine Paradigm; European Solid-State Circuits Conference `90, Grenoble, Frankreich 
Keyword: Reconfigurable logic Coprocessors
Quoted in:           
S. A. Guccione, M. J. Gonzales (E&CE Dept., Univ. of Texas, Austin): Classification and Performance of Reconfigurable Architectures; FPL´95 - Int´l Symposium on field-programmable Logic and Applications, Oxford, UK, 29-31 August 1995
[11] A. Ast, J. Becker, R. W. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Data-procedural Languages for FPL-based Machines; 4rd Int. Workshop On Field Programmable Logic And Applications, FPL’94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994 
Keyword: Reconfigurable architectures
Quoted in:         
B. K. Fawcett (Xilinx, Inc.): FPGAs as Configurable Computing Elements; Int´l Workshop on Reconfigurable Architectures @ IPPS´95 - 9th Int´l Parallel Processing Symposium, Santa Barbara, CA, 24-29 April 1995
[10] R. W. Hartenstein, editor, Hardware Description Languages, volume 7, chapter 3.3, pages 111; 136. Elsevier; Science Publishers, B.V. (North-Holland), 1987.
Keyword: Hardware Description Language
Quoted in:          
Elizabeth A. Walkup: Optimization of Linear Max-Plus Systems with Application to Timing Analysis; A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy; University of Washington; 1995
[9] Field-Programmable Logic: Architecture, Synthesis and Applications, R.W.Hartenstein, M.Servit (Eds.), Springer-Verlag, 1994, pp. 259-270.
Keyword: Field-Programmable Logic
Quoted in:         
Foundation for Research and Technology / Hellas, Institute of Computer Science, Crete, Greece; Computer Architecture and VLSI Systems Group; December 1994
[8] Lecture Notes in Comp. Sc. 705, Field Prog. Gate Arrays: Arch. and Tools for Rap. Prot., Grunbacher, H. and Hartenstein, R., eds., Springer-Verlag: Heidelberg, 1993, 152-161
Keyword: FPGA
Quoted in: 
Richard Halverson, Jr., Art Lew, University of Hawaii at Manoa, Honolulu, HI: Programming the Hawaii Parallel Computer; Proceedings of the 2nd ACM International Workshop on FPGAs, Berkeley, CA, Feb. 1994
[7] A. Ast, R. Hartenstein, R. Kress, H. Reinig, K. Schmidt, ?Novel High Performance Machine Paradigms and Fast Turnaround ASIC Design Methods: A Consequence of a Challenge to Field-programmable Logic, ? in Lecture Notes in Comp. Sc. 705, Field Prog. Gate Arrays: Arch and Tools for Rap. Prot., Grunbacher, H. and Hartenstein R., eds., Springer-Verlag, Heidelberg, 1993, pp. 210-217.
Keyword:
Quoted in:          
Richard Halverson, Jr. and Art Lew, University of Hawaii at Manoa, Honolulu, HI, 96822 (USA): Programming with Functional Memory; 1994 International Conference on Parallel Processing
[6] A. Ast, R. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Novel High Performance Machine Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and a Challenge to, Field-programmable Logic; Proceedings of the 2nd Int´ Workshop on Field-Programmable Logic and Applications, 31. 08. - 02. 09. 92, Vienna Austria: Lecture Notes on Computer Science: “FPGAs, Architectures and Tools for Rapid Prototyping”, Springer- Press, 1992
Keyword: Reconfigurable architectures
Quoted in:           
A. Koch, U. Golze (Technical University Braunschweig, Germany): A Universal Co-Processor for Workstations; in: W. R. Moore, W. Luk (eds.): More FPGAs; Abbington EE&CS Books, Oxford, UK 1993 (selection from Proc. Int´l Symposium on field-programmable Logic and Applications, Oxford, UK, Sept. 1993)
[5] R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London, 1989 
Keyword: Reconfigurable architectures
Quoted in:          
R. Gupta, G. De Micheli (Stanford University): Hardware-Software Cosynthesis for Digital Systems; IEEE Design & Test of Computers, Sept. 1993
[4] Reiner W. Hartenstein; Hardware Description Languages, volume 7 of Advances in CAD for VLSI, chapter 2; North-Holland, Amsterdam, 1987.
Keyword: Hardware Description Language
Quoted in:          
LIDEX Reference Manual, Jose Eduardo Moreira, Wilson Vicente Ruggiero; Departamento de Engenharia de Eletricidade, Escola Politencnica da Universidade de Sao Paulo, Brasil; Center for Supercomputing Research and Development, University of Illinois at Urban-Champaign, USA; Feruary 1990; CSRD Report No. 973
[3] Reiner W. Hartenstein: Hardware Description Languages, volume 7 of Advances in CAD for VLSI, chapter 1. North-Holland, Amsterdam, 1998
Keyword: Hardware Description Language
Quoted in:           
A Review of HDLs, Jose Eduardo Moreira, Wilson Vicente Ruggiero; Departamento de Engenharia de Eletricidade, Escola Politencnica da Universidade de Sao Paulo, Brasil; Center for Supercomputing Research and Development, University of Illinois at Urban-Champaign, USA; Feruary 1990; CSRD Report No. 971
[2] R. Hartenstein, A. Hirschbiel, M. Weber: A Flexible Architecture for Image Processing; Proceedings of EUROMICRO Symposium, Portsmouth, 1987
Keyword: scalable clustering of PUs .....
Quoted in:         
Ph. Treleaven, M. Pacheco, M. Vellasco: VLSI Architectures for VLSI Networks; IEEE Micro 9,6 (1989)
[1] Hartenstein R.W.; Koch G. The Universal Bus Considered Harmful in: R.W. Hartenstein and R. Zaks Microarchitecture of Computer Systems, North-Holland Publishing Co, 1975, 119-130.
Keyword:
Quoted in:           
Augusto Ciuffoletti: Using simple diffusion to synchronize the clocks in a distribited system; Dipartimento di Informatica, Universita di Pisa, Corso Itaia 40, 56125 Pisa (Italy)

last update in 1998